Memory device search system and method
First Claim
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1. A memory device, comprising:
- a main data memory for storing a plurality of entries in the memory device;
an address map and overflow data memory for storing an address map of the entries in the main data memory, the address map comprising an intended address location (IAL) and an actual physical location (APL) wherein the IAL indicates the external memory address of each entry and the APL indicates the actual memory locations for each entry within the memory device;
a controller for controlling the operation of the main data memory and the address map and overflow data memory using the IAL and APL in order to operate the memory device as one or more of a CAM and a RAM, the controller further comprising a comparator that compares each bit of an incoming piece of data with each bit of each entry of a bin in the memory device and search tree logic unit that sorts through the entries in the memory device to reduce the number of bit-by-bit comparisons performed by the comparator by selecting a bin of the memory device.
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Abstract
A search system and method is provided that may implemented in a content addressable memory (CAM) using various different memory technologies including SRAMs. DRAMs or Embedded DRAMs. The search system increases the density and efficiency of the CAM by using a search tree to reduce the total number of entries that must be matched against the key.
441 Citations
9 Claims
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1. A memory device, comprising:
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a main data memory for storing a plurality of entries in the memory device;
an address map and overflow data memory for storing an address map of the entries in the main data memory, the address map comprising an intended address location (IAL) and an actual physical location (APL) wherein the IAL indicates the external memory address of each entry and the APL indicates the actual memory locations for each entry within the memory device;
a controller for controlling the operation of the main data memory and the address map and overflow data memory using the IAL and APL in order to operate the memory device as one or more of a CAM and a RAM, the controller further comprising a comparator that compares each bit of an incoming piece of data with each bit of each entry of a bin in the memory device and search tree logic unit that sorts through the entries in the memory device to reduce the number of bit-by-bit comparisons performed by the comparator by selecting a bin of the memory device. - View Dependent Claims (2, 3, 4)
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5. A memory device, comprising:
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a main data memory for storing a plurality of entries in the memory device;
an address map and overflow data memory for storing an address map of the entries in the main data memory, the address map comprising an intended address location (IAL) and an actual physical location (APL) wherein the IAL indicates the external memory address of each entry and the APL indicates the actual memory locations for each entry within the memory device;
a controller for controlling the operation of the main data memory and the address map and overflow data memory using the IAL and APL in order to store and retrieve data from the memory device, the controller further comprising a comparator that compares each bit of an incoming piece of data with each bit of each entry in a bin of the memory device and search tree logic unit that sorts through the entries in the memory device to reduce the number of bit-by-bit comparisons performed by the comparator by selecting a bin of the memory device. - View Dependent Claims (6, 7, 8)
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9. A memory device, comprising:
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a main data memory for storing a plurality of entries in the memory device;
an address map and overflow data memory for storing an address map of the entries in the main data memory, the address map comprising an intended address location (IAL) and an actual physical location (APL) wherein the IAL indicates the external memory address of each entry and the APL indicates the actual memory locations for each entry within the memory device; and
a controller for controlling the operation of the main data memory and the address map and overflow data memory using the IAL and APL in order to store and retrieve data from the memory device, the controller further comprising an organizer that organizes the memory into a plurality of bins wherein each bin comprises a plurality of sub-bins and each sub-bin comprises a plurality of entries in the memory device, the bins and sub-bins having a least value and a most value associated with it that indicate a minimum value and a maximum value contained in the bin or sub-bin;
the controller further comprising a search tree logic unit that compares an incoming piece of data to the plurality of bins based on the least and most values to identify a bin in which the incoming piece of data is located and that compares the incoming piece of data to the sub-bins within the identified bin to determine the sub-bin that contains an entry matching the incoming piece of data.
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Specification