Formation of arrays of microelectronic elements

• US 6,391,658 B1
• Filed: 10/26/1999
• Issued: 05/21/2002
• Est. Priority Date: 10/26/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Scheuerlein, Roy E., Gates, Stephen M.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/427,251
• Time in Patent Office: 938 Days
• Field of Search: 438/3, 438/406, 438/407, 438/455, 438/766
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

Arrays of microelectronic elements such as magnetorestive memory elements and FET'"'"'s, including dual-gate FET'"'"'s, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

Claims

1. A method of forming an array of microelectronic elements, said method comprising:

preparing a first wafer of semiconductor material by implanting through a first surface of said first wafer, ions to a planar region at a selected depth therein, said ions being ions of an element selected from hydrogen and the noble gases;

preparing a second wafer of semiconductor material, said second wafer comprising a layer of dielectric material having a second surface, a pattern of mutually electrically isolated metal conductors being disposed within said layer, said metal conductors comprising spaced apart conducting regions extending to and being exposed at said second surface;

placing said first wafer over said second wafer with said first surface of said first wafer in juxtaposed adherence and electrical contact with said second surface and with exposed portions of said conducting regions;

inducing a fracture along said planar region of said first wafer to leave at least one semiconductor layer of said first wafer defined/bounded between said first surface and a fracture surface formed in said planar region, said first surface remaining in electrically contacting adherence with said second surface; and

using said at least one semiconductor layer to form a microelectronic element and positioning said microelectronic element in electrically contacting adherence to each of said mutually electrically isolated metal conductors.

2. The method as set forth in claim 1, wherein said microelectronic element comprises regions aligned with said metal conductors.

3. The method as set forth in claim 1, wherein said microelectronic element comprises a magnetoresistive memory element comprising a magnetic tunnel junction (MTJ) structure formed in electrical contact with said semiconductor layer above each of said conducting regions.

4. The method as set forth in claim 3, further comprising:

patterning said at least one semiconductor layer to form a diode over said conducting regions,

wherein said magnetic tunnel junction structure is in electrical contact with said diode.

5. The method as set forth in claim 4, wherein said magnetic tunnel junction structure comprises a fixed magnetic layer, a switchable magnetic layer, and a dielectric tunnel barrier formed between said fixed magnetic layer and said switchable magnetic layer.

6. A method of forming a microelectronic element, comprising:

implanting ions into a first semiconductor wafer;

forming isolated conductive layers in a second semiconductor wafer;

bonding said first semiconductor wafer to said second semiconductor wafer so that said conductive layers are in electrical contact with said first semiconductor wafer at a bonding interface;

fracturing said first semiconductor wafer substantially along a plane which is parallel to said bonding interface so that a portion of said first semiconductor wafer remains adhered to said second semiconductor wafer; and

using said portion of said first semiconductor wafer to form a microelectronic element and positioning said microelectronic element so that it electrically contacts said conductive layer of said second semiconductor wafer.

7. The method according to claim 6, wherein said ions comprise one of hydrogen ions and noble gas ions.

8. The method according to claim 6, wherein said portion of said first semiconductor wafer comprises a p-type semiconductor layer and an n-type semiconductor layer.

9. The method according to claim 8, wherein said p-type semiconductor layer and said n-type semiconductor layer are patterned to form diode mesas over said conductive layers.

10. The method according to claim 9, further comprising:

forming magnetic tunnel junction devices on said diode mesas.