Selectively activatable solar cells for integrated circuit analysis

• US 6,391,664 B1
• Filed: 09/29/1999
• Issued: 05/21/2002
• Est. Priority Date: 09/29/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Goruganthu, Rama R., Bruce, Michael R., Birdsley, Jeffrey D., Davis, Brennan V., Ring, Rosalinda M.
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/409,302
• Time in Patent Office: 965 Days
• Field of Search: 438/14, 438/15, 438/16, 438/17, 438/18, 438/19, 438/5, 438/7, 438/96, 438/97, 438/200
• US Class Current: 438/14
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

An integrated circuit manufacturing approach involves using a solar cell and facilitating post-manufacturing analysis. According to an example embodiment of the present invention, a solar cell is formed in an integrated circuit device and coupled to target circuitry in the device. The solar cell is activated and provides power to the target circuitry. In response to the solar cell providing power to the target circuitry, the integrated circuit is analyzed.

Claims

1. A method of manufacturing an integrated circuit device having target circuitry and of facilitating post-manufacturing analysis of the integrated circuit device, the method comprising:

forming a solar cell in the integrated circuit device;

coupling the solar cell to the target circuitry, wherein in response to light, the solar cell couples current to the target circuitry; and

packaging the integrated circuit and arranging the solar cell to be maintained unexposed to light, wherein during post-manufacturing analysis, the integrated circuit is accessed and the solar cell is exposed to light for analyzing the integrated circuit.

2. The method of claim 1, wherein analyzing the integrated circuit includes analyzing the target circuitry.

3. The method of claim 1, wherein the target circuitry includes at least one of:

a switch, suspect circuitry, and intervening circuitry arranged to drive circuitry to be analyzed.

4. The method of claim 1, wherein the integrated circuit is activated in response to input signals that are coupled to circuitry powered by the solar cell.

5. The method of claim 1, wherein the integrated circuit is part of a device having a back side opposite circuitry in a circuit side, wherein the solar cell is formed in the back side.

6. The method of claim 1, wherein the integrated circuit is part of a device having a back side opposite circuitry in a circuit side, and wherein the solar cell is formed in the circuit side.

7. The method of claim 1, wherein activating the solar cell includes directing light having photon energy greater than the band gap energy at the solar cell.

8. The method of claim 1, wherein activating the solar cell includes activating the target circuitry coupled to the solar cell.

9. The method of claim 1, wherein the target circuitry coupled to the solar cell includes a switch coupled to a power supply and other circuitry in the integrated circuit, and wherein activating the solar cell includes activating the switch and controlling the power supplied to the other circuitry in the integrated circuit via activating the switch.

10. The method of claim 1, wherein coupling the solar cell to target circuitry comprises forming vias in the integrated circuit device.

11. The method of claim 1, further comprising forming a contact in the integrated circuit device arranged for coupling the solar cell to the target circuitry.

12. The method of claim 1, wherein forming at least one solar cell comprises:

forming a n-doped region in the semiconductor device; and

forming a p-doped region in the n-doped region, wherein the p-doped region covers about all of one side of the n-doped region except a n-doped contact portion.

13. The method of claim 1, wherein activating at least one solar cell comprises:

directing light having a wavelength of about 1064 nanometers at the solar cell;

generating carriers in a depletion region at a p-n junction and creating electron-hole pairs; and

powering the device.

14. A method for manufacturing an integrated circuit device and facilitating post-manufacturing analysis, the method comprising:

forming bulk silicon having a front side and a back side;

forming a metal via in the bulk silicon;

polishing the front side of the bulk silicon;

forming a circuit layer having target circuitry on the polished front side of the bulk silicon and coupling the target circuitry to the metal via;

polishing the back side of the bulk silicon;

forming epitaxial silicon on the polished back side of the bulk silicon; and

forming a solar cell on the back side of the bulk silicon and coupling the solar cell to the metal via to facilitate activation of the target circuitry and analysis of the integrated circuit device.

15. The method of claim 14, wherein forming a solar cell on the back side of the bulk silicon comprises:

forming p-doped epitaxial silicon on the back side; and

forming an n-doped region over the p-doped epitaxial silicon.

16. The method of claim 15, wherein the epitaxial silicon includes amorphous silicon.

17. The method of claim 14, wherein forming a solar cell comprises bonding the solar cell to the back side of the bulk silicon.

18. The method of claim 14, wherein forming a solar cell includes forming a solar cell over about all of the back side of the bulk silicon.

19. The method of claim 14, wherein forming a metal via in the bulk silicon comprises:

milling the bulk silicon and forming a hole;

forming an insulative layer on the inside surface of the hole; and

forming a metal via in the insulated hole.