Method for identifying defective elements in array molding of semiconductor packaging

• US 6,391,666 B2
• Filed: 12/30/1999
• Issued: 05/21/2002
• Est. Priority Date: 12/30/1999
• Status: Expired due to Fees

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Liao, Chih-Chin, Huang, Ya-Hui, Her, Tzong-Dar
• Primary Examiner(s): Sherry, Michael J.
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US09/475,007
• Publication Number:
  US 20010051383A1
• Time in Patent Office: 873 Days
• Field of Search: 438/5-18, 700/90, 700/110, 700/121
• US Class Current: 438/15
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.

Claims

1. A method for identifying a defect in array molding of semiconductor packaging, comprising:

providing a plurality of dies;

providing a mini BGA packaging substrate having a circuit zone and a periphery zone surrounding the circuit zone, wherein the circuit zone has a plurality of package sites in array and is distinct from the periphery zone free from the package sites;

forming a plurality of marks only in the periphery zone of the packaging substrate, wherein the marks represent the locations of each of the package sites;

performing an inspection process to those package sites in order to find a defect in the package site;

labeling the mark that represents the location of the package site in the circuit zone where the defect is detected;

forming electrical connections between dies and the package sites respectively; and

performing a molding process by the use of a molding compound to cover the circuit zone with the periphery zone which has the marks being exposed.

2. The method for identifying defective elements in array molding of semiconductor packaging of claim 1 wherein the material employed by the mini BGA packaging substrate comprises Bismaleimide-Triazine (BT) epoxy.

3. The method for identifying defective elements in array molding of semiconductor packaging of claim 1 wherein those marks are formed in a two-dimensional coordinate array.

4. The method for identifying defective elements in array molding of semiconductor packaging of claim 1 wherein those marks are formed in a one-dimensional coordinate array.

5. The method for identifying defective elements in array molding of semiconductor packaging of claim 1 wherein a method to label a defective element is to draw a cross-wise line segment at the mark representing the defective element in the package sites.