Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique

• US 6,391,668 B1
• Filed: 05/01/2000
• Issued: 05/21/2002
• Est. Priority Date: 05/01/2000
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Harding, Brian E., Roy, Pradip K., Chetlur, Sundar S., Patel, Minesh A., Chacon, Carlos M.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US09/562,346
• Time in Patent Office: 750 Days
• Field of Search: 438/17, 438/471, 438/476, 438/197, 324/769
• US Class Current: 438/17
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.

Claims

1. A method of determining a trap density of a semiconductor substrate/dielectric interface, comprising:

measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, the measured current being a function of the number of traps located at the interface; and

determining the trap density as a function of the measured current.

2. The method as recited in claim 1 wherein measuring includes filling traps prior to the measuring.

3. The method as recited in claim 2 wherein filling traps includes depositing a charge on a surface of the dielectric layer to form a depletion region.

4. The method as recited in claim 3 wherein the substrate is doped with a p-type dopant and depositing a charge includes depositing a positive charge on the surface.

5. The method as recited in claim 3 wherein the substrate is doped with an n-type dopant and depositing a charge includes depositing a negative charge on the surface.

6. The method as recited in claim 3 further including forming a deep depletion region within the substrate by depositing a charge on the dielectric layer.

7. The method as recited in claim 6 wherein forming a deep depletion region includes depositing more of the charge on the surface of the dielectric layer.

8. The method as recited in claim 6 further including forming an accumulation region encompassed by the deep depletion region.

9. The method as recited in claim 8 wherein forming an accumulation region includes depositing an opposite charge through an opening in a guard ring and onto the surface to bring a portion of the deep depletion region into accumulation.

10. The method as recited in claim 8 wherein forming an accumulation region includes forming transient source/drain regions adjacent the accumulation region.

11. The method as recited in claim 1 wherein determining the trap density includes determining an interface trap charge (N_it) as a function of the current.

12. A method of fabricating an integrated circuit on a semiconductor wafer, comprising:

measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located at an interface of the semiconductor substrate and a dielectric layer, the measured current being a function of the number of traps located at the interface;

determining an electrical characterization as a function of the measured current;

adjusting a semiconductor wafer fabrication parameter if the electrical characterization falls outside a desired range;

forming transistors on the semiconductor wafer; and

interconnecting the transistors to form an operative integrated circuit.

13. The method as recited in claim 12 wherein measuring includes filling the traps prior to the measuring.

14. The method as recited in claim 13 wherein filling traps includes depositing a charge on a surface of the dielectric layer to form a depletion region.

15. The method as recited in claim 14 wherein the substrate is doped with a p-type dopant and depositing a charge includes depositing a positive charge on the surface.

16. The method as recited in claim 14 wherein the substrate is doped with an n-type dopant and depositing a charge includes depositing a negative charge on the surface.

17. The method as recited in claim 14 further including forming a deep depletion region within the substrate.

18. The method as recited in claim 17 wherein forming a deep depletion region includes depositing more of the charge on the surface of the dielectric layer.

19. The method as recited in claim 17 further including forming an accumulation region encompassed by the deep depletion region.

20. The method as recited in claim 19 wherein forming an accumulation region includes depositing an opposite charge through an opening in a guard ring and onto the surface to bring a portion of the deep depletion region into accumulation.

21. The method as recited in claim 20 wherein forming an accumulation region includes forming transient source/drain regions adjacent the accumulation region.

22. The method as recited in claim 12 wherein determining the electrical characterization includes determining an interface trap charge (N_it) as a function of the current.

23. A method of determining a trap density of a semiconductor substrate/dielectric interface, comprising:

filling traps located at the interface with minority carriers by forming a depletion region within a substrate;

collapsing at least a portion of the depletion region to either flatband or accumulation conditions; and

determining the trap density as a function of a current resulting from a recombination of majority carriers with the minority carriers that occurs at either the flatband or accumulation conditions.

24. The method as recited in claim 23 wherein filling traps includes depositing a charge on a surface of a dielectric layer to form the depletion region.

25. The method as recited in claim 23 wherein filling traps includes depositing a charge on a surface of the dielectric layer to form an inversion region.

26. The method as recited in claim 24 wherein the substrate is doped with a p-type dopant and depositing a charge includes depositing a positive charge on the surface.

27. The method as recited in claim 24 wherein the substrate is doped with an n-type dopant and depositing a charge includes depositing a negative charge on the surface.

28. The method as recited in claim 24 further including forming a deep depletion region within the substrate.

29. The method as recited in claim 28 wherein forming a deep depletion region includes depositing more of the charge on the surface of the dielectric layer.

30. The method as recited in claim 28 further including forming an accumulation region encompassed by the deep depletion region.

31. The method as recited in claim 30 wherein forming an accumulation region includes depositing a charge through an opening in a guard ring and onto the surface to bring a portion of the deep depletion region into accumulation.

32. The method as recited in claim 30 wherein forming an accumulation region includes forming transient source/drain regions adjacent the accumulation region.

33. The method as recited in claim 23 wherein determining the trap density includes determining an interface trap charge (N_it) as a function of the current.