Fabrication process for microstructure protection systems related to hard disk reading unit

• US 6,391,741 B1
• Filed: 07/14/2000
• Issued: 05/21/2002
• Est. Priority Date: 07/15/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Mastromatteo, Ubaldo, Zerbini, Sarah, Vigna, Benedetto, Sassolini, Simone
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): SARKAR, ASOK K
• Application Number:
  US09/616,227
• Time in Patent Office: 676 Days
• Field of Search: 735/040.9, 735/142.2, 735/142.3, 735/143.2, 735/143.6, 216/2, 257/254, 257/417, 257/418, 257/420, 310/90, 310/309, 359/198, 359/199, 359/212-214, 359/221, 359/223, 359/224, 359/226, 359/230, 360/97.01, 360/99.06, 360/99.08, 384/2-6, 438/50, 438/52, 438/455, 438/456, 438/458, 438/459, 438/460, 438/464, 438/481, 438/488, 438/593, 438/689, 438/704, 438/706, 438/712, 438/723
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: G11B 5/56 with provision for moving the head support for the purpose of adjusting the position of the head relative to the record carrier, e.g. manual adjustment for azimuth correction or track centering G11B5/52, G11B5/54, G11B5/58 take precedence
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

A process for assembling a microactuator on a R/W transducer that includes forming a first wafer of semiconductor material having a plurality of microactuators including suspended regions and fixed regions separated from each other by first trenches; forming a second wafer of semiconductor material comprising blocking regions connecting mobile and fixed intermediate regions separated from each other by second trenches; bonding the two wafers so as to form a composite wafer wherein the suspended regions of the first wafer are connected to the mobile intermediate regions of the second wafer, and the fixed regions of the first wafer are connected to the fixed intermediate regions of the second wafer; cutting the composite wafer into a plurality of units; fixing the mobile intermediate region of each unit to a respective R/W transducer; and removing the blocking regions. The blocking regions are made of silicon oxide, and the intermediate regions are made of polycrystalline silicon.

Claims

1. A process for assembling a group of elements having at least one first element and one second element, said first element including a microstructure without package, the process comprising:

forming a first wafer of semiconductor material comprising a plurality of microstructures including first and second operating regions separated from each other by first trenches,

forming a second wafer of semiconductor material comprising blocking regions connecting a plurality of first and second intermediate regions, said first and second intermediate regions separated from each other by second trenches;

joining said first wafer and second wafer to form a composite wafer wherein said first operating regions are fixed to said first intermediate regions, and said second operating regions are fixed to said second intermediate regions;

cutting said composite wafer into a plurality of units, each unit including at least one first operating region and one second operating region, and one first intermediate region and one second intermediate region;

fixing said first intermediate region of at least one unit to said second element; and

removing said blocking regions.

2. The process of claim 1 wherein forming a second wafer comprises forming at least one blocking layer, and after said joining, the process further comprises partially removing said blocking layer so as to form said blocking regions at least at said second trenches.

3. The process of claim 2 wherein forming a second wafer comprises:

forming a substrate of semiconductor material;

forming said blocking layer on top of said substrate;

forming a semiconductor layer on top of said blocking layer; and

forming said second trenches in said semiconductor layer to obtain said first and second intermediate regions.

4. The process of claim 3, further comprising forming cavities in said semiconductor layer, said cavities delimiting projecting portions in said first and second intermediate regions, and wherein joining comprises bonding said projecting portions to said first and second operating regions.

5. The process of claim 3 wherein said substrate is made of polycrystalline silicon;

and forming a blocking layer comprises forming a silicon oxide layer; and

forming a semiconductor layer comprises epitaxially growing a polycrystalline silicon layer.

6. The process of claim 3, further comprising, before joining said first wafer and said second wafer, reducing the thickness of said substrate.

7. The process of claim 3, further comprising, before cutting, completely removing said substrate.

8. The process of claim 7 wherein completely removing said substrate comprises mechanically reducing the thickness of said substrate and subsequently completely etching said substrate.

9. The process of claim 8 wherein mechanically reducing is carried out by grinding, and completely etching is carried out by wet etching or plasma etching.

10. The process of claim 7, further comprising, before cutting, forming conductive regions extending over said blocking regions and said first and second intermediate regions.

11. The process of claim 10 wherein said conductive regions comprise electrical connection lines and metallic regions, said electrical connection lines extending over said blocking regions and said second trenches, and said metallic regions extending over said first intermediate regions;

and wherein fixing comprises bonding said second element to a metallic region extending over said first intermediate region of said at least one unit.

12. The process of claim 10, further comprising, after said step of forming conductive regions, forming electrical connection structures between said second element and said conductive regions.

13. The process of claim 1, further comprising, before removing said blocking regions, fixing said unit to a supporting element.

14. The process of claim 13 wherein fixing said unit to a supporting element comprises bonding a substrate region of said first wafer to said supporting element.

15. The process of claim 14, further comprising, after said step of bonding, electrically connecting said second element and said first wafer to said supporting element.

16. The process of claim 1 wherein said blocking regions are made of silicon oxide and wherein removing said blocking regions comprises etching said silicon oxide in hydrofluoric acid gas.

17. The process of claim 1 wherein said unit belongs to a hard disk reading unit, said microstructure comprises a microactuator, and said second element comprises a read/write transducer.