Method for bottomless deposition of barrier layers in integrated circuit metallization schemes

• US 6,391,785 B1
• Filed: 08/23/2000
• Issued: 05/21/2002
• Est. Priority Date: 08/24/1999
• Status: Expired due to Term

• Current Assignee: ASM International NV, Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: ASM Microchemistry Oy (ASM International NV), Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Elers, Kai-Erik, Haukka, Suvi P., Maex, Karen, Soininen, Pekka Juha, Saanila, Ville Antero, Satta, Alessandra
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nhu, David
• Application Number:
  US09/644,636
• Time in Patent Office: 636 Days
• Field of Search: 438/622, 438/633, 438/637, 438/638, 438/648, 438/650, 438/680, 438/681, 438/683, 438/685, 438/687, 438/656, 438/667, 438/672, 438/689, 438/692, 438/704, 438/715, 438/745, 438/706, 438/763
• US Class Current: 438/704
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/08 from metal halides
• CPC Class Codes: C23C 16/32 Carbides
• CPC Class Codes: C23C 16/44 characterised by the method of coating C23C16/04 takes precedence
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/02 Elements
• CPC Class Codes: C30B 29/36 Carbides
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 : Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.

Claims

1. A method of selectively depositing a layer using an atomic layer deposition process, the method comprising;

providing a deposition substrate comprising a first insulating surface and a second surface, the first and second surfaces having different material compositions; and

selectively coating over the first surface as compared to the second surface by repeatedly alternating exposure of the deposition substrate to at least two reactant fluids.

2. The method of claim 1, wherein the first surface is formed by an insulating material that is selectively coated and the second surface is formed by a conductor.

3. The method of claim 2, wherein the first surface defines an opening in an insulating layer within an integrated circuit and the second surface comprises a metal element exposed by the opening.

4. The method of claim 2, wherein selectively coating comprises depositing a barrier material over the insulating material.

5. The method of claim 4, wherein the barrier material is conductive and has a resistivity less than about 300 μ

Ω

-cm.

6. The method of claim 4, wherein the barrier material comprises a metal nitride.

7. The method of claim 6, wherein the barrier material comprises titanium nitride.

8. The method of claim 4, wherein the barrier material is an insulator.

9. The method of claim 1, further comprising conditioning at least the first surface for reaction with the reactant fluids.

10. The method of claim 9, wherein conditioning comprises forming ligands selectively on the first surface.

11. The method of claim 9, wherein conditioning comprises forming ligands on the first surface and the second surface and subsequently modifying the ligands on the second surface.

12. The method of claim 11, wherein modifying the ligands comprises converting the ligands into a growth-blocking layer.

13. The method of claim 11, wherein modifying the ligands comprises removing the ligands selectively from the second surface.

14. The method of claim 13, wherein removing the ligands selectively comprises heating the substrate.

15. The method of claim 14, wherein removing the ligands selectively further comprises exposing the substrate to a reducing ambient.

16. The method of claim 14, wherein removing the ligands selectively further comprises subjecting the substrate to a vacuum.

17. The method of claim 14, wherein removing the ligands selectively further comprises subjecting the substrate to high pressure.

18. The method of claim 13, wherein removing the ligands selectively comprises a chemical reduction.

19. The method of claim 13, wherein removing the ligands comprises cleaning the second surface.

20. The method of claim 9, wherein conditioning comprises exposing the substrate to moisture.

21. The method of claim 9, wherein the first surface comprises a form of oxide and conditioning comprises exposing the substrate to a source H or OH radicals.

22. The method of claim 9, wherein conditioning comprises forming ligands on the first surface selected from the group consisting of hydroxyl, cyano, NH₂, NH, fluoro, bromo, iodo, chloro, methyl, alkoxo, β

-diketonato and isopropoxo.

23. The method of claim 1, further comprising forming a sacrificial layer over the second surface prior to coating the first surface.

24. The method of claim 23, wherein the sacrificial layer comprises a material susceptible to etching from exposure to the at least two reactant fluids.

25. The method of claim 1, wherein providing comprises plasma etching an opening in an insulating layer to expose a metallic element, thereby producing the first surface on the insulating layer with conditioning ligands thereupon and the second surface on the metallic element without conditioning ligands thereupon.

26. A method of selectively forming a barrier layer over insulating sidewalls of an opening in a partially fabricated integrated circuit, comprising:

forming ligands over insulating surfaces of the partially fabricated integrated circuit, leaving conductive surfaces exposed; and

introducing vapor-phase reactants to react with the ligands over the insulating surfaces to selectively deposit a barrier material over the insulating surfaces.

27. The method of claim 26, wherein introducing vapor-phase reactants comprises alternatingly introducing at least first and second vapor-phase reactants in an atomic layer deposition process.

28. The method of claim 26, wherein the ligands are selected from the group consisting of hydroxyl, cyano, NH₂, NH, fluoro, bromo, iodo, chloro, methyl, alkoxo, β

-diketonato, isopropoxo.

29. The method of claim 26, further comprising removing the ligands from the conductive surfaces.

30. The method of claim 29, wherein removing the ligands comprises reducing.

31. The method of claim 26, wherein forming ligands comprises exposing the insulating surfaces to moisture.

32. The method of claim 26, wherein forming ligands comprises forming hydroxyl tails.