Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces

• US 6,392,253 B1
• Filed: 08/06/1999
• Issued: 05/21/2002
• Est. Priority Date: 08/10/1998
• Status: Expired due to Fees

• Current Assignee: Arjun J. Saxena
• Original Assignee: Arjun J. Saxena
• Inventors: Saxena, Arjun J.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/370,100
• Time in Patent Office: 1,019 Days
• Field of Search: 257/50, 257/59, 257/51, 257/63-66, 257/750, 257/736, 257/347
• US Class Current: 257/59
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A monolithically integrated, multi-layer device is fabricated with single crystal films of desired orientation grown from arrayed nucleation sites on amorphous and/or non-single crystal surfaces. Examples of devices which can be produced are CMOS and bipolar devices in single crystal (100) and (111) Si films on amorphous surfaces such as SiO2 or Si3N4 in processed ULSIC wafers. These devices can be integrated along the 3rd dimension. Thus, 3-dimensional IC'"'"'s can be fabricated. Similarly, high performance CMOS devices in SiGe films, MESFET, HEMT and optical devices in compound semiconductor films, can be fabricated within processed ULSIC wafers. Further, Si—, GaAs—, and other compound semiconductor-based devices in the respective single crystal films with different orientations deposited selectively in a given level, and in multilevel IC'"'"'s, can be manufactured. Solar cells of high efficiency, large area flat panel displays, TV, single crystal films of high Tc superconductors, metals and insulators can be fabricated for a variety of microelectronic and other applications, such as for remote communications with outside systems without requiring metal wiring between the systems.

Claims

1. A monolithic device comprising a plurality of monolithically integrated layers including at least:

(a) a first layer; and

(b) a second layer, disposed above the first layer and operatively coupled to the first layer for communicating with the first layer;

wherein;

(a.1) said first layer includes a respective first single crystal material grown from a corresponding first set of spaced-apart nucleation-friendly sites whose apart spacings correspond to whole number multiples of respective lattice constants of the first single crystal material, and the spaced-apart nucleation-friendly sites of the first set thereby substantially define a first growth template which seeded growth of said first single crystal material therefrom, where each first nucleation-friendly site in said first set is defined by one or more first particles to which the material of the first single crystal material attaches more preferentially than to first surrounding material surrounding the first nucleation-friendly site, the first surrounding material being nucleation-unfriendly to the material of the first single crystal material;

(b.1) said second layer includes a respective second single crystal material grown from a corresponding second set of spaced-apart nucleation-friendly sites whose apart spacings correspond to whole number multiples of respective lattice constants of the second single crystal material, and the spaced-apart nucleation-friendly sites of the second set thereby substantially define a second growth template which seeded growth of said second single crystal material therefrom, where each second nucleation-friendly site in said second set is defined by one or more second particles to which the material of the second single crystal material attaches more preferentially than to second surrounding material surrounding the second nucleation-friendly site, the second surrounding material being nucleation-unfriendly to the material of the second single crystal material.

3. A multilayer monolithic device as set forth in claim 1, wherein each of the first and second layers has opposed surfaces with one of the surfaces having a respective single crystal material provided thereat and the other of the opposed surfaces having an insulator provided thereat.

4. A multilayer monolithic device as set forth in claim 1, wherein the first and second single crystal materials respectively define respective, but different semiconductor materials.

5. The multilayer monolithic device of claim 4, wherein the different semiconductor materials include two or more selected from the group consisting of:

(ab.1) silicon having a (100) orientation of crystal planes;

(ab.2) silicon having a (111) orientation of crystal planes;

(ab.3) GaAs;

(ab.4) GaAlAs;

(ab.5) GaP; and

(ab.6) SiGe.

6. A device as set forth in claim 1, wherein the first and second single crystal materials each respectively define at least one of single crystal silicon and single crystal compound semiconductor films grown on arrayed nucleation sites, wherein the arrayed nucleation sites are defined in respective ones of amorphous materials.

7. A device as set forth in claim 1, wherein at least one of said first and second single crystal materials is grown from a corresponding set of nucleation-friendly sites exposed on a surface of a SiO₂ layer.

8. A device as set forth in claim 1, wherein at least one of said first and second single crystal materials is grown from a corresponding set of nucleation-friendly sites disposed in an amorphous material.

9. A device as set forth in claim 1, wherein at least one of the first and second single crystal materials is grown from a corresponding set of nucleation-friendly, silicon sites disposed in an amorphous material.

10. A device as set forth in claim 1, wherein at least one of the first and second single crystal materials is grown from a corresponding set of nucleation-friendly sites disposed in Si₃N₄.

11. A device as set forth in claim 1, wherein at least one of the first and second single crystal materials is grown from a corresponding set of nucleation-friendly sites exposed from a surface of an amorphous material and is structured to have a (100) crystal orientation.

12. A device as set forth in claim 1, wherein at least one of the first and second single crystal materials is grown from a corresponding set of nucleation-friendly sites provided within a recessed region defined in a non-single crystal substrate.

13. A multilayer monolithic device as set forth in claim 1, wherein at least one of the first and second single crystal materials defines a single crystal gate of, and/or a single crystal local interconnect to a field effect transistor of the device.

14. A device as set forth in claim 1, wherein the first and second single crystal materials respectively define a respective first and second member of the group consisting of:

CMOS circuitry, BICMOS circuitry, and bipolar circuitry.

15. A multilaver monolithic device as set forth in claim 1, wherein at least one of the first and second single crystal materials defines a single crystal SiGe film having varying concentrations of Ge provided thereacross for defining both CMOS and bipolar devices.

16. A multilayer monolithic device as set forth in claim 1, wherein at least one of the first and second single crystal materials defines a single crystal insulator.

17. The multilayer monolithic device of claim 16, wherein the single crystal insulator defines an inter-layer dielectric (ILD) within the multilayer monolithic device.

18. The multilayer monolithic device of claim 16, wherein the single crystal insulator defines a passivation layer protecting lower layers of the multilayer monolithic device from contamination.

19. A multilayer monolithic device as set forth in claim 1, wherein at least one of the first and second single crystal materials is disposed on an amorphous glass that is used for a flat panel display.

20. A multilayer monolithic device a set forth in claim 1, wherein at least one of the first and second single crystal defines an optical waveguide that is monolithically integrated within said device for suporting optical communications.

21. The multilayer monolithic device of claim 1, wherein said SCANS devices are selected from the group consisting of NMOS transistors, PMOS transistors, bipolar transistors, MESFETs, HEMTs, and electro-optical devices.

22. A multilayer monolithic device a set forth in claim 1, wherein at least one of the first and second single crystal materials defines a single crystal metal connector that serves as an interlayer interconnector between layers of said device.

23. A multilayer monolithic device a set forth in claim 1, wherein the second single crystal material defines optical devices which allow optical communicating with outside systems.

24. The multilayer monolithic device of claim 1, wherein the said first and second single crystal materials respectively define transistor gates within their respective first and second layers.

25. The multilayer monolithic device of claim 1, wherein the said first and second single crystal materials respectively define SCANS devices (devices fabricated in Single Crystal films grown on Arrayed Nucleation Sites on amorphous or non-single crystal surfaces) within their respective first and second layers.

26. The multilayer monolithic device of claim 1, wherein at least one of the said first and second single crystal materials is respectively defined within a recessed region of, and is coplanar to a surface of a non-single crystal material that is further provided within the respective first or second layer of the at least one single crystal material.

2. A multilayer monolithic device as set forth in claimed 1, wherein the said first and second single crystal materials respectively define local interconnects within their respective first and second layers.

27. A monolithic device comprising a plurality of monolithically integrated layers including at least:

(a) a first layer; and

(b) a second layer, disposed above the first layer and operatively coupled to the first layer for communicating with the first layer;

wherein;

(a.1) said first layer includes a respective first single crystal material defining active electronic components;

(b.1) said second layer includes a respective second single crystal material grown from a set of spaced-apart nucleation-friendly sites whose apart spacings correspond to whole number multiples of respective lattice constants of the second single crystal material, and the spaced-apart nucleation-friendly sites thereby substantially define a growth template which seeded growth of said second single crystal material therefrom, where each nucleation-friendly site is defined by one or more particles to which the material of the second single crystal material attaches more preferentially than to surrounding material surrounding the nucleation-friendly site, the surrounding material being nucleation-unfriendly to the material of the second single crystal material.