Input buffer circuit for RF phase-locked loops

• US 6,392,452 B2
• Filed: 01/12/2000
• Issued: 05/21/2002
• Est. Priority Date: 01/13/1999
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-Oh
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US09/481,158
• Publication Number:
  US 20020000843A1
• Time in Patent Office: 860 Days
• Field of Search: 327/63, 327/65, 327/66, 327/103, 327/108-112, 327/432, 327/563, 327/427, 327/478, 326/26, 326/27, 326/82-84, 326/85, 330/311, 330/252, 330/254
• US Class Current: 327/108
• CPC Class Codes: H03K 19/01812 with at least one differential stage
• CPC Class Codes: H03K 5/2409 using bipolar transistors H03K5/2436 takes precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers. In addition, the bandwidth can be controlled by resistors as an equivalent active inductance of the input buffer circuit. Further, the input buffer circuit can reduce the power consumption compared with conventional input buffer circuits, since the input buffer circuit according to the present invention uses a first switching current of the first amplifier as well as a second switching current of the second amplifier to load output signals.

Claims

1. An input buffer circuit of a prescaler for pre-dividing an oscillating signal having a radio band frequency in a frequency divider of a radio frequency phase-locked loop (RF PLL), the input buffer circuit comprising:

switching circuit receiving a first switching current from a power supply voltage source, switching the first switching current in response to the oscillating signal, and generating first and second switching signals by converting the first switching current into first and second switching voltages;

second switching means for receiving a second switching current from the power supply voltage source and switching the second switching current, in response to the first and the second switching signals;

loading means coupled to the second switching means for generating third and fourth switching signals by converting both the first and second switching currents into third and fourth switching voltages; and

output driving means for outputting first and second output signals in response to the third and fourth switching signals, respectively.

2. The input buffer circuit of claim 1, wherein:

the loading section of the first switching means provides the first and second switching signals to the second switching means by converting the first switching current into the first and the second switching voltages in response to the switching operation of the switching circuit of the first switching means; and

the cascode transistors are in cascode with the loading section to supply the first switching current for the switching circuit through the loading section without loss.

3. The input buffer circuit of claim 2, wherein the switching circuit comprises:

a first switching transistor, having a control electrode to receive an inverted oscillating signal and a bias current, and a current path, for switching the first switching current in response to the inverted oscillating signal;

a second switching transistor, having a control electrode to receive the oscillating signal and a bias current, and a current path, for switching the first switching current in response to the oscillating signal, wherein the oscillating signal is a non-inverted oscillating signal;

a first resistor for delivering the bias current from a first bias voltage source into the control electrode of the first switching transistor;

a second resistor for delivering the bias current from the first bias voltage source into the control electrode of the second switching transistor; and

a current sinker coupled between the current paths of the first and second switching transistors and a ground voltage source, for sinking the first switching current in response to the switching operation of the first and second switching transistors.

4. The input buffer circuit of claim 3, wherein the cascode circuit comprises:

a first cascode transistor, having a control electrode to receive a bias current and a current path coupled to the loading section, for supplying the first switching current for the loading section without loss;

a second cascode transistor, having a control electrode to receive a bias current and a current path coupled to the loading section, for supplying the first switching current for the loading section without loss;

a third resistor for delivering the bias current from a second bias voltage source into the control electrode of the first cascode transistor; and

a fourth resistor for delivering the bias current from the second bias voltage source into the control electrode of the second cascode transistor.

5. The input buffer circuit of claim 4, wherein the third and the fourth resistors are worked as an equivalent inductance when the frequency of the oscillating signal is high, so that the output bandwidth of the input buffer circuit can be controlled by the resistors.

6. The input buffer circuit of claim 4, wherein the loading section comprises:

a fifth resistor, coupled between the current path of the first cascode transistor and the current path of the first switching transistor, for delivering the first switching current from the first cascode transistor to the first switching transistor and generating the first switching signal in response to the switching operation of the first switching transistor; and

a sixth resistor, coupled between the current path of the second cascode transistor and the current path of the second switching transistor, for delivering the first switching current from the second cascode transistor to the second switching transistor and generating the second switching signal in response to the switching operation of the second switching transistor.

7. The input buffer circuit of claim 3, wherein the second switching means comprises:

a third switching transistor, having a control electrode to receive the first switching signal from the first switching means and a current path, for switching the second switching current in response to the first switching signal;

a fourth switching transistor, having a control electrode to receive the second switching signal from the first switching means and a current path, for switching the second switching current in response to the second switching signal; and

a current sinker coupled between the current paths of the third and fourth switching transistors and the ground voltage source, for sinking the second switching current in response to the switching operation of the third and fourth switching transistors.

8. The input buffer circuit of claim 7, wherein the loading means comprises:

a first loading resistor coupled between the power supply voltage source and the current paths of the second cascode transistor and the third switching transistor, for generating the third switching signal by converting both the first and the second switching currents into the third switching voltage in response to the switching operation of the second switching means; and

a second loading resistor coupled between the power supply voltage source and the current paths of the first cascode transistor and the fourth switching transistor, for generating the fourth switching signal by converting both the first and the second switching currents into the fourth switching voltage in response to the switching operation of the second switching means.

9. The input buffer circuit of claim 3, wherein the output driving means comprises:

a first output transistor having a control electrode to receive the third switching signal, and a current path coupled between the power supply voltage source and a first output terminal, wherein the first output terminal outputs the first output signal of the input buffer circuit in response to the third switching signal;

a second output transistor having a control electrode to receive the fourth switching signal, and a current path coupled between the power supply voltage source and a second output terminal, wherein the second output terminal outputs the second output signal of the input buffer circuit in response to the fourth switching signal;

a third current sinker coupled between the first output electrode and the ground voltage source, for sinking a current from the current path of the first output transistor; and

a fourth current sinker coupled between the second output electrode and the ground voltage source, for sinking a current from the current path of the second output transistor.

10. The input buffer circuit of claim 1, wherein the first switching means, second switching means, and output driving means comprise a plurality of bipolar junction transistors (BJTs).

11. An input buffer circuit of a prescaler for pre-dividing an oscillating signal having a radio band frequency in a frequency divider of a radio frequency phase-locked loop (RF PLL), the input buffer circuit comprising:

first switching means including a loading circuit and cascode transistors in cascode with the loading circuit, for receiving a first switching current from a power supply voltage source, switching the first switching current in response to the oscillating signal, and generating a first and a second switching signal by converting the first switching current into a first and a second switching voltage;

second switching means for receiving a second switching current from the power supply voltage source and switching the second switching current, in response to the first and the second switching signal;

loading means coupled to the second switching means for generating a third and a fourth switching signal by converting both the first and the second switching currents into a third and a fourth switching voltage; and

output driving means for outputting a first and a second output signal in response to the third and the fourth switching signal, respectively, wherein;

the first switching means comprises a switching circuit for selectively switching the first switching current in response to the oscillating signal;

the loading circuit generates the first and the second switching signal into the second switching means by converting the first switching current into the first and the second switching voltage, respectively, in response to the switching operation of the switching circuit; and

the cascode transistors are in a cascode circuit in cascode with the loading circuit for supplying the first switching current for the switching circuit through the loading circuit without loss, the switching circuit comprising;

a first switching transistor, having a control electrode to receive an inverted oscillating signal and a bias current, and a current path, for switching the first switching current in response to the inverted oscillating signal;

a second switching transistor, having a control electrode to receive the oscillating signal and a bias current, and a current path, for switching the first switching current in response to the oscillating signal, wherein the oscillating signal is a non-inverted oscillating signal;

a first resistor for delivering the bias current from a first bias voltage source into the control electrode of the first switching transistor;

a second resistor for delivering the bias current from the first bias voltage source into the control electrode of the second switching transistor; and

a current sinker coupled between the current paths of the first and second switching transistors and a ground voltage source, for sinking the first switching current in response to the switching operation of the first and second switching transistors.

12. The input buffer circuit of claim 11, wherein the cascode circuit comprises:

a first cascode transistor, having a control electrode to receive a bias current and a current path coupled to the loading circuit, for supplying the first switching current for the loading circuit without loss;

a second cascode transistor, having a control electrode to receive a bias current and a current path coupled to the loading circuit, for supplying the first switching current for the loading circuit without loss;

a third resistor for delivering the bias current from a second bias voltage source into the control electrode of the first cascode transistor; and

a fourth resistor for delivering the bias current from the second bias voltage source into the control electrode of the second cascode transistor.

13. The input buffer circuit of claim 12, wherein the third and the fourth resistors are worked as an equivalent inductance when the frequency of the oscillating signal is high, so that the output bandwidth of the input buffer circuit can be controlled by the resistors.

14. The input buffer circuit of claim 12, wherein the loading circuit comprises:

a fifth resistor, coupled between the current path of the first cascode transistor and the current path of the first switching transistor, for delivering the first switching current from the first cascode transistor to the first switching transistor and generating the first switching signal in response to the switching operation of the first switching transistor; and

a sixth resistor, coupled between the current path of the second cascode transistor and the current path of the second switching transistor, for delivering the first switching current from the second cascode transistor to the second switching transistor and generating the second switching signal in response to the switching operation of the second switching transistor.

15. The input buffer circuit of claim 11, wherein the second switching means comprises:

a third switching transistor, having a control electrode to receive the first switching signal from the first switching means and a current path, for switching the second switching current in response to the first switching signal;

a fourth switching transistor, having a control electrode to receive the second switching signal from the first switching means and a current path, for switching the second switching current in response to the second switching signal; and

a current sinker coupled between the current paths of the third and fourth switching transistors and the ground voltage source, for sinking the second switching current in response to the switching operation of the third and fourth switching transistors.

16. The input buffer circuit of claim 15, wherein the loading means comprises:

a first loading resistor coupled between the power supply voltage source and the current paths of the second cascode transistor and the third switching transistor, for generating the third switching signal by converting both the first and the second switching currents into the third switching voltage in response to the switching operation of the second switching means; and

a second loading resistor coupled between the power supply voltage source and the current paths of the first cascode transistor and the fourth switching transistor, for generating the fourth switching signal by converting both the first and the second switching currents into the fourth switching voltage in response to the switching operation of the second switching means.

17. The input buffer circuit of claim 11, wherein the output driving means comprises:

a first output transistor having a control electrode to receive the third switching signal, and a current path coupled between the power supply voltage source and a first output terminal, wherein the first output terminal outputs the first output signal of the input buffer circuit in response to the third switching signal;

a second output transistor having a control electrode to receive the fourth switching signal, and a current path coupled between the power supply voltage source and a second output terminal, wherein the second output terminal outputs the second output signal of the input buffer circuit in response to the fourth switching signal;

a third current sinker coupled between the first output electrode and the ground voltage source, for sinking a current from the current path of the first output transistor; and

a fourth current sinker coupled between the second output electrode and the ground voltage source, for sinking a current from the current path of the second output transistor.