Semiconductor integrated circuit

• US 6,392,467 B1
• Filed: 07/10/2000
• Issued: 05/21/2002
• Est. Priority Date: 10/24/1996
• Status: Expired due to Fees

• Current Assignee: Toshiba Corporation
• Original Assignee: Toshiba Corporation
• Inventors: Oowaki, Yukihito, Fuse, Tsuneaki
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/612,679
• Time in Patent Office: 680 Days
• Field of Search: 323/281, 326/112, 326/113, 327/77, 327/89, 327/530, 327/534, 327/535, 327/537, 327/427
• US Class Current: 327/427
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence

Abstract

A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

Claims

1. A semiconductor circuit having a NMOS pass gate network and a buffer circuit coupled to said NMOS pass gate network, said input of said buffer being coupled to an output of said pass gate network said NMOS pass gate network having a NMOSFET wherein an input signal for said NMOSFET is applied to the gate and body of said NMOSFET;

and

a voltage regulation means to regulate the voltage applied to said semiconductor circuit wherein said regulated voltage is lower than 0.8 V.

2. A semiconductor integrated circuit, as claimed in claim 1, wherein said NMOSFET is formed on a silicon layer formed on an insulated layer (SOI).

3. A semiconductor integrated circuit, as claimed in claim 1, wherein a PMOS flip flop circuit is connected to input of said buffer circuit.

4. A semiconductor integrated circuit as claimed in claim 2 wherein a PMOS flip flop circuit is connected to input said buffer circuit.

5. A semiconductor integrated circuit having a main circuit comprising a NMOS pass gate network and a buffer circuit coupled to said NMOS pass gate network, said NMPOS pass gate network having a NMOSFET wherein an input signal for said NMOSFET is applied to the gate and body of said NMOSFET;

and

a charge pump circuit coupled to said main circuit to generate a high voltage, wherein said charge pump is composed of capacitor and NMOSFET'"'"'s gate electrode and body of at least one of said NMOSFETs are directly connected.

6. A semiconductor integrated circuit, as claimed in claim 5, wherein body electrode of each of said NMOSFETs is electrically separated individually.

7. A semiconductor integrated circuit, as claimed in claim 5, wherein said MOSFET is formed on a silicon layer formed on an insulated layer (SOI).

8. A semiconductor integrated circuit, as claimed in claim 5, including a voltage regulation means to regulate the voltage applied to NMOS pass gate network wherein said regulated voltage is lower than 0.8V.

9. A semiconductor integrated circuit as claimed in claim 6 including a voltage regulation means to regulate the voltage applied to NMOS pass gate network wherein said regulated voltage is lower than 0.8V.

10. A semiconductor integrated circuit as claimed in claim 7 including a voltage regulation means to regulate the voltage applied to NMOS pass gate network wherein said regulated voltage is lower than 0.8V.