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High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers

  • US 6,392,490 B1
  • Filed: 08/28/2000
  • Issued: 05/21/2002
  • Est. Priority Date: 08/31/1999
  • Status: Expired due to Term
First Claim
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1. A biasing circuit for a CMOS cascode stage with inductive load and degeneration, the cascode stage comprising at least one first MOS transistor and at least one second MOS transistor serially connected between a first voltage reference and a second voltage reference, the biasing circuit comprising:

  • at least one first MOS replica transistor matched to the at least one first MOS transistor and connected thereto, the at least one first MOS replica transistor comprising a gate, source and drain;

    at least one second MOS replica transistor matched to the at least one second MOS transistor and connected to the first voltage reference, the at least one second MOS replica transistor comprising a gate, source and drain;

    a respective current generator for biasing each of said at least one first and second MOS replica transistors; and

    a detection circuit for detecting a voltage on the source of said at least one second MOS replica transistor and for applying a voltage to the gate of said at least one first replica MOS transistor.

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