High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers
First Claim
1. A biasing circuit for a CMOS cascode stage with inductive load and degeneration, the cascode stage comprising at least one first MOS transistor and at least one second MOS transistor serially connected between a first voltage reference and a second voltage reference, the biasing circuit comprising:
- at least one first MOS replica transistor matched to the at least one first MOS transistor and connected thereto, the at least one first MOS replica transistor comprising a gate, source and drain;
at least one second MOS replica transistor matched to the at least one second MOS transistor and connected to the first voltage reference, the at least one second MOS replica transistor comprising a gate, source and drain;
a respective current generator for biasing each of said at least one first and second MOS replica transistors; and
a detection circuit for detecting a voltage on the source of said at least one second MOS replica transistor and for applying a voltage to the gate of said at least one first replica MOS transistor.
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Accused Products
Abstract
A high-precision biasing circuit is provided for a CMOS cascode stage with inductive load and degeneration. The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The biasing circuit includes at least a first MOS replica transistor and a second MOS replica transistor, and two current generators for biasing the first and second MOS replica transistors. A circuit block detects a voltage value on a terminal of the second replica MOS transistor and applies a voltage to a gate terminal of the first replica transistor. Two circuit block implementations include a voltage amplifier and a folded cascode amplifier closed in a shunt feedback. Both implementations allow the threshold voltages of the cascode stage transistors to be tracked, as well as their Early and body effects.
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Citations
27 Claims
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1. A biasing circuit for a CMOS cascode stage with inductive load and degeneration, the cascode stage comprising at least one first MOS transistor and at least one second MOS transistor serially connected between a first voltage reference and a second voltage reference, the biasing circuit comprising:
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at least one first MOS replica transistor matched to the at least one first MOS transistor and connected thereto, the at least one first MOS replica transistor comprising a gate, source and drain;
at least one second MOS replica transistor matched to the at least one second MOS transistor and connected to the first voltage reference, the at least one second MOS replica transistor comprising a gate, source and drain;
a respective current generator for biasing each of said at least one first and second MOS replica transistors; and
a detection circuit for detecting a voltage on the source of said at least one second MOS replica transistor and for applying a voltage to the gate of said at least one first replica MOS transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A biasing circuit for a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference, the biasing circuit comprising:
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a first replica transistor matched to the first transistor and connected thereto, the first replica transistor comprising a control terminal and a conduction terminal;
a second replica transistor matched to the second transistor and connected to the first voltage reference, the second replica transistor comprising a control terminal and a conduction terminal;
a first current generator for biasing said first replica transistor;
a second current generator for biasing said second replica transistor; and
a detection circuit for detecting a voltage value on the conduction terminal of said second replica transistor and for applying a voltage to the control terminal of said first replica transistor. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. An amplifier comprising:
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a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference;
a biasing circuit connected to said cascode stage and comprising a first replica transistor matched to said first transistor and connected thereto, said first replica transistor comprising a control terminal and a conduction terminal, a second replica transistor matched to said second transistor and connected to the first voltage reference, said second replica transistor comprising a control terminal and a conduction terminal, a first current generator for biasing said first replica transistor, a second current generator for biasing said second replica transistor, and a detection circuit for detecting a voltage value on the conduction terminal of said second replica transistor and for applying a voltage to the control terminal of said first replica transistor. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method for biasing a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference, the method comprising:
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biasing a first replica transistor matched to the first transistor and connected thereto, the first replica transistor comprising a control terminal and a conduction terminal;
biasing a second replica transistor matched to the second transistor and connected to the first voltage reference, the second replica transistor comprising a control terminal and a conduction terminal;
detecting a signal on the conduction terminal of the second replica transistor; and
applying a predetermined bias to the control terminal of the first replica transistor based upon the detected signal. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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Specification