Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode

• US 6,392,909 B1
• Filed: 03/27/2001
• Issued: 05/21/2002
• Est. Priority Date: 09/20/2000
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Tae-jin, Jang, Tae-seong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/818,876
• Publication Number:
  US 20020034115A1
• Time in Patent Office: 420 Days
• Field of Search: 365/201, 365/225.7, 365/233
• US Class Current: 365/225.7
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.

Claims

1. A semiconductor memory device, comprising:

a master signal generator for generating a master signal in response to one of a power-up signal and a latency test signal;

a plurality of fuse information units for generating fuse information signals in response to one of the power-up signal, the master signal and a combination thereof;

a plurality of mode register set (MRS) address information units which receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal; and

a CAS latency determining unit for generating CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide one of a fixed CAS latency during first mode of operation of the semiconductor device and varying CAS latencies during a second mode of operation of the semiconductor device.

2. The semiconductor memory device of claim 1, wherein the master signal generator comprises:

a fuse program unit responsive to the power-up signal, wherein the fuse program unit comprises a first fuse for programming the fuse program unit;

a latency test enable unit for generating the master signal in response to the output of the fuse program unit and the latency test signal; and

a buffer for generating an inverted signal of the master signal.

3. The semiconductor memory device of claim 2, wherein the fuse program unit further comprises:

an inverter for receiving the power-up signal;

a PMOS transistor, operatively coupled between a supply voltage and the first fuse, responsive to the output of the inverter; and

an NMOS transistor, operatively coupled between a ground voltage and the first fuse, which generates an output signal of the fuse program unit in response to the output of the inverter.

4. The semiconductor memory device of claim 2, wherein the latency test enable unit comprises:

a NOR gate which generates the master signal in response to an output of the fuse program unit and the latency test signal; and

an NMOS transistor, operatively coupled between the output of the fuse program unit and a ground voltage, and being responsive to the master signal.

5. The semiconductor memory device of claim 1, wherein each fuse information unit comprises:

a fuse program unit responsive to the power-up signal, wherein the fuse program unit comprises a second fuse for programming the fuse program unit;

a fuse information signal generator for generating the fuse information signal in response to the output of the fuse program unit and the master signal; and

a buffer for generating an inverted signal of the fuse information signal.

6. The semiconductor memory device of claim 5, wherein the fuse program unit further comprises:

an inverter for receiving the power-up signal;

a PMOS transistor, operatively coupled between a supply voltage and the second fuse, responsive to the output of the inverter; and

an NMOS transistor, operatively coupled between a ground voltage and the second fuse, for generating the output signal of the fuse program unit in response to the output of the inverter.

7. The semiconductor memory device of claim 5, wherein the fuse information signal generator comprises:

a NOR gate for generating the fuse information signal in response to the output of the fuse program unit and the master signal; and

an NMOS transistor, operatively coupled between the output of the fuse program unit and a ground voltage, responsive to the fuse information signal.

8. The semiconductor memory device of claim 1, wherein each MRS address information unit comprises:

a first transmitter for transmitting an address bit in response to the address window signal;

a first latch for latching the output of the first transmitter;

a second transmitter for transmitting the output of the first latch in response to the MRS addressing signal;

a second latch for latching the output of the second transmitter; and

a buffer for generating the MRS address latch signal in response to the output of the second latch.

9. The semiconductor memory device of claim 8, wherein each MRS address information unit further comprises a setting unit for initializing the first and second latches in response to an initial state of the power-up signal.

10. The semiconductor memory device of claim 1, wherein the CAS latency determining unit comprises:

a fuse coding unit for encoding the fuse information signals;

an MRS address coding unit for encoding the MRS address information signals and outputting the encoded result in response to the master signal; and

a determining unit for generating a CAS latency in response to the output of the fuse coding unit and the MRS address coding unit.

11. The semiconductor memory device of claim 10, wherein the fuse coding unit comprises:

a NAND gate for receiving the fuse information signals; and

an inverter, connected to the output of the NAND gate, for generating an output signal of the fuse coding unit.

12. The semiconductor memory device of claim 10, wherein the MRS address coding unit comprises:

a NAND gate for receiving the MRS address latch signals; and

a NOR gate for generating an output signal of the MRS address coding unit in response to the output of the NAND gate and the master signal.

13. The semiconductor memory device of claim 10, wherein the determining unit generates the CAS latency in response to the output of the fuse coding unit and the output of the MRS address coding unit.

14. A semiconductor memory device, comprising

a first circuit for generating a first control signal and a complementary first control signal in response to a power-up signal and a latency test signal;

a second circuit, responsive to the complementary first control signal, for generating a plurality of second control signals;

a third circuit, responsive to an address signal, for generating a plurality of third control signals; and

a fourth circuit, responsive to the first control signal, for selectively processing the second control signals and third control signals to provide one of a fixed CAS latency during a first mode of operation of the semiconductor device and a plurality of CAS latencies during a second mode of operation of the semiconductor device.

15. The semiconductor memory device of claim 14, wherein the first and second circuits are fuse programmable.

16. The semiconductor memory device of claim 14, wherein the third circuit comprises a MRS (mode set register) address circuit.

17. The semiconductor memory device of claim 14, wherein the second control signals are indicative of a fixed CAS latency.

18. The semiconductor memory device of claim 14, wherein the third control signals are indicative of a dynamically selected CAS latency.

19. A method for providing a CAS latency in a semiconductor memory device, comprising the steps of:

generating a first control signal indicative of a fixed CAS latency;

generating a second control signal indicative of one of a plurality of non-fixed CAS latencies;

selectively processing one of the first and second control signals during one of a first mode of operation of the semiconductor device to provide the fixed CAS latency and a second mode of operation of the semiconductor device to provide one of the non-fixed CAS latencies.