Circuit for eliminating idle cycles in a memory device
First Claim
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1. A memory device, comprising:
- a memory array;
an address circuit coupled to the memory array, wherein the address circuit includes;
an address register;
a burst logic coupled to the address register;
a first write address register coupled to the burst logic;
a second write address register coupled to the first write address register;
a first compare circuit coupled to the address register and the first write address register;
a second compare circuit coupled to the address register and the second write address register; and
a first selective connector coupled to the second write address register and the memory array; and
a read circuit coupled to the memory array;
a write circuit coupled to the memory array, wherein the write circuit includes;
a first data input register;
a second data input register coupled to the first data input register;
a selective connector coupled to the first data input register and the second data input register; and
a write driver coupled to the selective connector; and
a control circuit coupled to the address circuit, the read circuit, and the write circuit.
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Abstract
A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.
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Citations
27 Claims
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1. A memory device, comprising:
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a memory array;
an address circuit coupled to the memory array, wherein the address circuit includes;
an address register;
a burst logic coupled to the address register;
a first write address register coupled to the burst logic;
a second write address register coupled to the first write address register;
a first compare circuit coupled to the address register and the first write address register;
a second compare circuit coupled to the address register and the second write address register; and
a first selective connector coupled to the second write address register and the memory array; and
a read circuit coupled to the memory array;
a write circuit coupled to the memory array, wherein the write circuit includes;
a first data input register;
a second data input register coupled to the first data input register;
a selective connector coupled to the first data input register and the second data input register; and
a write driver coupled to the selective connector; and
a control circuit coupled to the address circuit, the read circuit, and the write circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory device, comprising:
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a memory array;
an address circuit coupled to the memory array;
a read circuit coupled to the memory array, wherein the read circuit includes;
a sense amplifier coupled to the memory array;
a first selective connector coupled to the sense amplifier;
an output register coupled to the first selective connector;
a second selective connector coupled to the output register; and
an output buffer coupled to the second selective connector; and
a write circuit coupled to the memory array, wherein the write circuit includes;
a first data input register;
a second data input register coupled to the first data input register;
a selective connector coupled to the first data input register and the second data input register; and
a write driver coupled to the selective connector; and
a control circuit coupled to the address circuit, the read circuit, and the write circuit. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A memory device, comprising:
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a memory array;
an address circuit coupled to the memory array;
a read circuit coupled to the memory array;
a write circuit coupled to the memory array, wherein the write circuit includes;
a first data input register;
a second data input register coupled to the first data input register;
a selective connector coupled to the first data input register and the second data input register; and
a write driver coupled to the selective connector; and
a control circuit coupled to the address circuit, the read circuit, and the write circuit, wherein the control circuit includes;
first and second input enable registers, wherein the first and second input enable registers are coupled to the write circuit;
first and second read enable registers, wherein the first and second read enable registers are coupled to the read circuit;
an output bypass register coupled to the second input enable register and the first read enable register; and
a write register coupled to the write circuit. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A memory device, comprising:
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a memory array;
an address circuit coupled to the memory array;
a read circuit coupled to the memory array;
a write circuit coupled to the memory array, wherein the write circuit includes;
a first data input register;
a second data input register coupled to the first data input register;
a selective connector coupled to the first data input register and the second data input register; and
a write driver coupled to the selective connector; and
a control circuit coupled to the address circuit, the read circuit, and the write circuit, wherein the control circuit includes;
first and second input enable registers, wherein the first and second input enable registers are coupled to the write circuit;
first and second read enable registers, wherein the first and second read enable registers are coupled to the read circuit;
an output bypass register coupled to the second input enable register and the first read enable register;
a write register coupled to the write circuit; and
a byte write circuit coupled to the write circuit. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification