Booth multiplier with low power, high performance input circuitry

• US 6,393,454 B1
• Filed: 08/31/1999
• Issued: 05/21/2002
• Est. Priority Date: 01/30/1995
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Chu, Tam-Anh
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/387,636
• Time in Patent Office: 994 Days
• Field of Search: 708/630, 708/625
• US Class Current: 708/630
• CPC Class Codes: G06F 7/5338 each bitgroup having two new bits, e.g. 2nd order MBA

Abstract

A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array. The split bus has a first branch that provides the first number unbuffered to the top row of the array, and a second branch having a buffer circuit and providing the first number buffered to the other rows of the array. The buffer circuit has low-power, low-speed buffers since the top row is able to receive the first number unbuffered, and the remaining rows in the array do not need to receive the first number until after the top row of adder cells completes its addition.

Claims

1. A Booth multiplier for multiplying a first number with a second number to produce a product, comprising:

an array of adder cells arranged in a plurality of rows of adder cells, the adder cells performing addition on bits of the first and second numbers, one of the adder cells of each row being a left-most cell for that row, each row of adder cells receiving Booth recoded control signals formed from a different subset of bits of the second number, each of the adder cells in each row receiving a different bit of the first number;

wherein said array of adder cells comprises rows of an integer multiple of sixteen adder cells, and a first one of said rows receives bits of one of the first and second numbers without said bit being buffered; and

a plurality of Booth recoding logic cells, each Booth recoding logic cell coupled to the left-most cell of a different one of the rows, the Booth recoding logic cells receiving different subsets of bits of the second number and generating the Booth recoded control signals as a function of the received subset of bits;

wherein at least one Booth recoding logic cell includes balanced logic circuitry for ensuring that all of the Booth recoded control signals from that Booth recoding logic cell are outputted from the Booth recoding logic cell at substantially the same time while an output adder receives inputs which do not arrive at substantially the same time.

2. A Booth multiplier for multiplying a first number with a second number to produce a product, comprising:

an array of adder cells arranged in a plurality of rows of adder cells, the adder cells performing addition on bits of the first and second numbers, one of the adder cells of each row being a left-most cell for that row, each row of adder cells receiving Booth recoded control signals formed from a different subset of bits of the second number, each of the adder cells in each row receiving a different bit of the first number;

wherein said array of adder cells comprises rows of an integer multiple of sixteen adder cells, and a first one of said rows and a plurality of the adder cells receive bits of one of the first and second numbers without said bit being buffered and receives a second of the first and second numbers buffered; and

a plurality of Booth recoding logic cells, each Booth recoding logic cell coupled to the left-most cell of a different one of the rows, the Booth recoding logic cells receiving different subsets of bits of the second number and generating the Booth recoded control signals as a function of the received subset of bits;

wherein at least one Booth recoding logic cell includes balanced logic circuitry for ensuring that all of the Booth recoded control signals from that Booth recoding logic cell are outputted from the Booth recoding logic cell at substantially the same time while an output adder receives inputs which do not arrive at substantially the same time.

3. A Booth multiplier for multiplying a first number with a second number to produce a product, comprising:

an array of adder cells arranged in a plurality of rows of adder cells, the adder cells performing addition on bits of the first and second numbers, one of the adder cells of each row being a left-most cell for that row, each row of adder cells receiving Booth recoded control signals formed from a different subset of bits of the second number, each of the adder cells in each row receiving a different bit of the first number;

wherein said array of adder cells comprises rows of an integer multiple of sixteen adder cells, and a first one of said rows receives bits of one of the first and second numbers without said bit being buffered and at least subsequent rows of adder cells receive a second of the first and second numbers buffered; and

a plurality of Booth recoding logic cells, each Booth recoding logic cell coupled to the left-most cell of a different one of the rows, the Booth recoding logic cells receiving different subsets of bits of the second number and generating the Booth recoded control signals as a function of the received subset of bits;

wherein at least one Booth recoding logic cell includes balanced logic circuitry for ensuring that all of the Booth recoded control signals from that Booth recoding logic cell are outputted from the Booth recoding logic cell at substantially the same time while an output adder receives inputs which do not arrive at substantially the same time.

4. The Booth multiplier of claim 3 wherein the first row of adder cells receives the second of the first and second numbers unbuffered.

5. A Booth multiplier for multiplying a first number with a second number to produce a product, comprising:

an array of adder cells arranged in a plurality of rows of adder cells, the adder cells performing addition on bits of the first and second numbers, one of the adder cells of each row being a left-most cell for that row, each row of adder cells receiving Booth recoded control signals formed from a different subset of bits of the second number, each of the adder cells in each row receiving a different bit of the first number;

wherein said array of adder cells comprises rows of a like number of adder cells, and a first one of said rows receives bits of one of the first and second numbers without said bit being buffered and at least subsequent rows of adder cells receive a second of the first and second numbers buffered; and

a plurality of Booth recoding logic cells, each Booth recoding logic cell coupled to the left-most cell of a different one of the rows, the Booth recoding logic cells receiving different subsets of bits of the second number and generating the Booth recoded control signals as a function of the received subset of bits;

wherein at least one Booth recoding logic cell includes balanced logic circuitry for ensuring that all of the Booth recoded control signals from that Booth recoding logic cell are outputted from the Booth recoding logic cell at substantially the same time while an output adder receives inputs which do not arrive at substantially the same time.

6. The Booth multiplier of claim 5 wherein the first row of adder cells receives the second of the first and second numbers unbuffered.

7. The Booth multiplier of claim 5 wherein the delay minimizes temporary short-circuit paths within the adder cells.