System and method for initiating a serial data transfer between two clock domains

• US 6,393,502 B1
• Filed: 08/31/1999
• Issued: 05/21/2002
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Meyer, Derrick R., Madrid, Philip Enrique
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/386,650
• Time in Patent Office: 994 Days
• Field of Search: 710/58, 710/61, 713/400, 713/401, 713/600, 365/221, 375/354
• US Class Current: 710/58
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver. One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

Claims

1. A method for communicating a serial data stream between a transmitter and a receiver, wherein the transmitter operates according to at least a first clock having a first clock rate, wherein the receiver operates according to at least a second clock having a second clock rate, wherein a ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one, the method comprising:

storing a start bit in a first storage element in response to the first clock;

storing a ratio bit in a second storage element in response to the first clock subsequent to said storing the start bit in the first storage element;

sampling the start bit in response to the second clock;

sampling the ratio bit in response to the second clock;

detecting the start bit following said sampling the start bit in response to the second clock; and

sampling subsequent bits following the ratio bit at a rate dependent upon said ratio bit.

2. The method of claim 1, further comprising:

storing the start bit in a third storage element following said sampling the start bit in response to the second clock; and

storing the ratio bit in a fourth storage element following said sampling the ratio bit in response to the second clock.

3. The method of claim 2, wherein said receiver is further configured to operate according to a fast clock having a fast clock rate, wherein the ratio of the fast clock rate to the second clock is a second integer number greater than 1, the method further comprising:

sampling the start bit in response to the fast clock;

storing the start bit in a fifth storage element following said sampling the start bit in response to the fast clock;

sampling the ratio bit in response to the fast clock; and

storing the ratio bit in a sixth storage element following said sampling the ratio bit in response to the fast clock.

4. The method of claim 3, wherein said sampling the start bit in response to the fast clock and said sampling the ratio bit in response to the fast clock occur concurrently on an edge of the fast clock.

5. The method of claim 4, wherein said sampling the start bit in response to the fast clock and said sampling the ratio bit in response to the fast clock occur a predetermined period of time after said storing the start bit in the third storage element and the predetermined period of time after said storing the ratio bit in the fourth storage element.

6. The method of claim 1, wherein said first storage element and said second storage are one storage element, the method further comprising:

storing the start bit in another storage element concurrently with said storing the ratio bit in the second storage element.

7. A method for initializing a serial data stream between a transmitter and a receiver, wherein the transmitter operates according to at least a first clock having a first clock rate, wherein the receiver operates according to at least a second clock having a second clock rate, wherein a ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one, the method comprising:

storing a start bit in a first storage element in response to the first clock;

storing a ratio bit in a second storage element in response to the first clock subsequent to said storing the start bit in the first storage element;

sampling the start bit in response to the second clock;

sampling the ratio bit in response to the second clock;

detecting the start bit following said sampling the start bit in response to the second clock; and

determining a rate for sampling a remainder of said serial data stream dependent upon said ratio bit.

8. The method of claim 7, further comprising:

storing the start bit in a third storage element following said sampling the start bit in response to the second clock; and

storing the ratio bit in a fourth storage element following said sampling the ratio bit in response to the second clock.

9. The method of claim 8, wherein said receiver is further configured to operate according to a fast clock having a fast clock rate, wherein the ratio of the fast clock rate to the second clock is a second integer number greater than 1, the method further comprising:

sampling the start bit in response to the fast clock;

storing the start bit in a fifth storage element following said sampling the start bit in response to the fast clock;

sampling the ratio bit in response to the fast clock; and

storing the ratio bit in a sixth storage element following said sampling the ratio bit in response to the fast clock.

10. The method of claim 9, wherein said sampling the start bit in response to the fast clock and said sampling the ratio bit in response to the fast clock occur concurrently on an edge of the fast clock.

11. The method of claim 10, wherein said sampling the start bit in response to the fast clock and said sampling the ratio bit in response to the fast clock occur a predetermined period of time after said storing the start bit in the third storage element and the predetermined period of time after said storing the ratio bit in the fourth storage element.

12. The method of claim 7, wherein said first storage element and said second storage are one storage element, the method further comprising:

storing the start bit in another storage element concurrently with said storing the ratio bit in the second storage element.

13. An apparatus for receiving a serial data stream clocked at a first clock rate, wherein said apparatus is configured to operate according to a fast clock rate that is a multiple of a second clock rate, wherein a ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one, the apparatus comprising:

a first register coupled to receive the serial data stream, wherein said first register is configured to latch bits upon an edge of a clock operating at said first clock rate;

a second register coupled to receive an output of said first register, wherein said second register is configured to latch bits upon an edge of said clock operating at said first clock rate;

a third register coupled to receive an output of said first register, wherein said third register is configured to latch bits upon an edge of a clock operating at said second clock rate;

a fourth register coupled to receive an output of said second register, wherein said fourth register is configured to latch bits upon an edge of said clock operating at said second clock rate;

a fifth register coupled to receive an output of said third register, where said fifth register is enabled only for a predetermined period after said edge of said clock that latches said third register, wherein said fifth register is configured to latch bits upon an edge of said fast clock;

a sixth register coupled to receive an output of said fourth register, where said sixth register is enabled only for a predetermined period after said edge of said clock that latches said fourth register, wherein said sixth register is configured to latch bits upon an edge of said fast clock;

logic coupled to receive an output of said fifth register and said sixth register, wherein said serial data stream begins with a start bit indicating a state on a serial line different from an initial state on said serial line, wherein said start bit is followed by a ratio bit indicating a ratio between said second clock rate and said first clock rate, wherein said logic receives said ratio bit from said fifth register concurrently with receiving said start bit from said sixth register, wherein said logic adjusts said predetermined period based on a decode of said ratio bit.

14. The apparatus of claim 13, wherein said first register and said second register latch on a rising edge of said clock operating at said first clock rate.

15. The apparatus of claim 13, wherein said third register and said fourth register latch on a falling edge of said clock operating at said second clock rate.

16. The apparatus of claim 13, wherein said fifth register and said sixth register latch on either edge of said fast clock.