Virtual channel bus and system architecture

• US 6,393,506 B1
• Filed: 06/15/1999
• Issued: 05/21/2002
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kenny, John D.
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/334,144
• Time in Patent Office: 1,071 Days
• Field of Search: 710/107-125, 710/305
• US Class Current: 710/113
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A processor system includes an on-chip, split-transaction bus with independent address/control and data buses. Arbitration and bus acquisition protocols are performed on the address/control bus. An arbiter arbitrates I/O requests and regulates concurrent ownership of the split-transaction bus by assigning a virtual channel to each bus request. Data bus access is granted to a virtual channel on a priority basis, s so as to utilize to a maximum extent the available bandwidth of the data bus. In one embodiment, the data bus is preempted by another virtual channel when current virtual channel using the data bus becomes idle due to, for example, latencies in the data stream. Rearbitration, however, is avoided when the interrupted data transfer resumes, owing to state information regarding the data transfer stored in the master and slave modules of each virtual channel.

Claims

1. A computer system including a shared bus, said shared bus including a control portion and a data portion, said system comprising:

an arbiter for assigning a plurality of virtual channels and for granting access to said data portion of said shared bus to one of said virtual channels; and

a plurality of functional modules each including;

i) an interface circuit for reading from and writing to said shared bus;

ii) a memory address counter for tracking data transfer progress on said data portion of shared bus; and

iii) a register for storing control information relating to a virtual channel.

2. A computer as in claim 1 wherein said arbiter assigns each of said virtual channels a priority based on which said arbiter grants access to said data portion of said shared bus.

3. A computer system as in claim 2 wherein said priority scheme is preemptive priority.

4. A computer system as in claim 3 wherein said priority is fixed.

5. A computer system as in claim 3, wherein said priority is dynamically allocated.

6. A computer system as in claim 1 further comprising a plurality of buffers to be associated with said virtual channels for prefetching data from said memory.

7. A computer system as in claim 1, wherein, when one of said functional modules requests one of said virtual channel for communicating with a targeted one of said functional modules, said arbiter assigns a virtual channel to said requesting functional module and said targeted functional module.

8. A computer system as in claim 7, wherein, when said requesting and targeted functional modules are ready for data transfer, one of said requesting and targeted functional modules asserts a data ready signal associated with said assigned virtual channel.

9. A computer system as in claim 8, wherein said arbiter grants access to said data portion of said shared bus upon detecting said data ready signal and upon determining that said data portion of said shared bus is available.

10. A method for transferring data between functional modules in a modularized computer system having a plurality of functional modules, and a shared bus, said shared bus having a control portion and a data portion, said method comprising the steps of:

a) assigning a virtual channel to a selected pair of said functional modules;

b) storing control information of said virtual channel in each module of selected pair of said functional modules;

c) granting access to said data portion of said bus by said assigned virtual channel, when one of said selected pair of said functional modules asserts a data ready signal associated with said assigned virtual channel and when said data portion of said bus is available; and

d) tracking data transfer progress using address registers in each module of said selected pair of said functional modules.

11. A method as in claim 10, further comprising the steps of:

a) providing a priority scheme among virtual channels;

b) granting access to said data portion of said shared bus to a first virtual channel in accordance with said priority scheme;

c) monitoring data transfer in said first virtual channel, wherein when said first virtual channel becomes idle, granting access to said data portion of said shared bus to a second virtual channel having a priority less than said first virtual channel; and

d) granting access to said data portion of said shared bus to said first virtual channel when said first virtual channel ceases to be idle.

12. A method as in claim 11, further comprising the steps of:

a) providing a plurality of buffers in a memory subsystem;

b) assigning a buffer to each of said first and said second virtual channels; and

c) fetching data from said memory subsystem into each of said assigned buffers for placing on said data portion of said shared bus whenever the associated one of said first and second virtual channels is granted access to said data portion of said shared bus.