Multi-stream associative memory architecture for computer telephony
First Claim
1. A communications circuit coupled to at least one time division multiplexed bus carrying a plurality of data streams of time division multiplexed time slot data, the communications circuit comprising:
- a plurality of content addressable memory blocks coupled to respective portions of the plurality of data streams of the time division multiplexed bus and configured to associate indicia of data storage locations with time slots of the respective streams; and
time division multiplexed communications interface circuitry coupled to the plurality of content addressable memory blocks and configured to switch time division multiplexed time slot data from a first of the data streams to a second of the data streams using the content addressable memory blocks.
9 Assignments
0 Petitions
Accused Products
Abstract
Aspects of the present invention are directed to communications circuits and method that utilize associative memories for providing telephony switching of data between different time slots in one or more time division multiplexed (TDM) serial data lines or streams. The communications circuit may include a first content-addressable memory block and a second content-addressable memory block each of which receive the same address for independently generating tags for accessing a data memory to provide data to or receive data from TDM data lines.
-
Citations
14 Claims
-
1. A communications circuit coupled to at least one time division multiplexed bus carrying a plurality of data streams of time division multiplexed time slot data, the communications circuit comprising:
-
a plurality of content addressable memory blocks coupled to respective portions of the plurality of data streams of the time division multiplexed bus and configured to associate indicia of data storage locations with time slots of the respective streams; and
time division multiplexed communications interface circuitry coupled to the plurality of content addressable memory blocks and configured to switch time division multiplexed time slot data from a first of the data streams to a second of the data streams using the content addressable memory blocks. - View Dependent Claims (2, 3)
-
-
4. A switch for use with a time division multiplexed bus carrying a plurality of data streams of time division multiplexed time slot data, the switch comprising:
-
a first memory storing a plurality of indications of data storage locations, the indications associated with respective first-memory locations, the first memory configured to output an indication corresponding to a selected first-memory location;
a second memory including a plurality of data storage locations, the second memory coupled to the first memory and configured to select a data storage location, indicated by the indication output by the first memory and received by the second memory, for data transfer between the selected data storage location and the time division multiplexed bus. - View Dependent Claims (5, 6, 7, 8, 9)
-
-
10. A telecommunications switching method comprising:
-
receiving a first indication, associated with a data storage area of a data portion of memory circuitry, by at least one of a plurality of content addressable memories included in the memory circuitry;
transferring time slot data from a time division multiplexed bus to the data storage area in response to the first indication;
receiving a second indication, associated with the data storage area, by at least one of the plurality of content addressable memories included in the memory circuitry; and
transferring time slot data from the data storage area to the time division multiplexed bus in response to the second indication. - View Dependent Claims (11, 12, 13, 14)
-
Specification