Multi-stream associative memory architecture for computer telephony

• US 6,393,515 B1
• Filed: 01/06/2000
• Issued: 05/21/2002
• Est. Priority Date: 09/16/1997
• Status: Expired due to Term

• Current Assignee: Dialogic, Inc. (Enghouse Systems Limited)
• Original Assignee: NMS Communications Corporation (Live Microsystems, Inc.)
• Inventors: Pollack, Jonathan D., Linton, Charles C.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/478,253
• Time in Patent Office: 866 Days
• Field of Search: 370/401, 370/442, 370/347, 370/337, 370/352, 370/321, 370/322, 370/382, 370/400, 711/101, 711/202, 711/207, 711/108
• US Class Current: 711/108
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

Aspects of the present invention are directed to communications circuits and method that utilize associative memories for providing telephony switching of data between different time slots in one or more time division multiplexed (TDM) serial data lines or streams. The communications circuit may include a first content-addressable memory block and a second content-addressable memory block each of which receive the same address for independently generating tags for accessing a data memory to provide data to or receive data from TDM data lines.

Claims

1. A communications circuit coupled to at least one time division multiplexed bus carrying a plurality of data streams of time division multiplexed time slot data, the communications circuit comprising:

a plurality of content addressable memory blocks coupled to respective portions of the plurality of data streams of the time division multiplexed bus and configured to associate indicia of data storage locations with time slots of the respective streams; and

time division multiplexed communications interface circuitry coupled to the plurality of content addressable memory blocks and configured to switch time division multiplexed time slot data from a first of the data streams to a second of the data streams using the content addressable memory blocks.

2. The communications circuit of claim 1 wherein the first data stream is different from the second data stream.

3. The communications circuit of claim 1 wherein each of the plurality of content addressable memory blocks is coupled to at least one data memory configured to store data from, and supply data to, the time division multiplexed bus.

4. A switch for use with a time division multiplexed bus carrying a plurality of data streams of time division multiplexed time slot data, the switch comprising:

a first memory storing a plurality of indications of data storage locations, the indications associated with respective first-memory locations, the first memory configured to output an indication corresponding to a selected first-memory location;

a second memory including a plurality of data storage locations, the second memory coupled to the first memory and configured to select a data storage location, indicated by the indication output by the first memory and received by the second memory, for data transfer between the selected data storage location and the time division multiplexed bus.

5. The switch of claim 4 wherein the first memory includes a plurality of content addressable memories, the first-memory locations store addresses, and the data storage locations store tags.

6. The switch of claim 4 wherein the first memory includes a plurality of content addressable memories and a pipeline memory.

7. The switch of claim 6 wherein the content addressable memories each include first-memory locations that store content addressable memory addresses that are associated with pipeline addresses, and wherein the pipeline memory includes tags associated with the pipeline addresses, the tags being indicative of the data storage locations.

8. The switch of claim 4 further comprising control circuitry configured to select first-memory locations of the first memory and to cause data to be transferred between a time division multiplexed bus and a selected data storage location of the second memory to cause data to be transferred between streams of data of the time division multiplexed bus.

9. The switch of claim 4 wherein the indicia of data storage locations are one of data storage location tags and physical addresses of a pipeline memory that stores data storage location tags at the physical addresses.

10. A telecommunications switching method comprising:

receiving a first indication, associated with a data storage area of a data portion of memory circuitry, by at least one of a plurality of content addressable memories included in the memory circuitry;

transferring time slot data from a time division multiplexed bus to the data storage area in response to the first indication;

receiving a second indication, associated with the data storage area, by at least one of the plurality of content addressable memories included in the memory circuitry; and

transferring time slot data from the data storage area to the time division multiplexed bus in response to the second indication.

11. The method of claim 10 wherein time slot data are transferred from a first stream of the bus in response to the first indication and time slot data are transferred to a second stream of the bus in response to the second indication, the first stream being different than the second stream.

12. The method of claim 10 wherein the second indication is received by a content addressable memory that is different from a content addressable memory that receives the first indication.

13. The method of claim 10 wherein the at least one content addressable memory that receives the first indication transfers a tag associated with the first indication to the data portion of the memory circuitry.

14. The method of claim 10 wherein the at least one content addressable memory that receives the first indication transfers a physical address to a pipeline memory portion of the memory circuitry and the pipeline memory portion transfers a tag associated with the first indication to the data portion of the memory circuitry in response to receiving the physical address.