Load/store unit employing last-in-buffer indication for rapid load-hit-store
First Claim
1. A load/store unit comprising:
- a buffer including a plurality of entries, each of said plurality of entries configured to store a data address and a last-in-buffer (LIB) indication, wherein said LIB indication, in a first state, is indicative that a corresponding store memory operation is a youngest store memory operation within said buffer to update a memory location identified by said data address; and
control logic coupled to said buffer and to receive a first data address probing a data cache, wherein said control logic is configured to identify a first entry of said plurality of entries for which;
(i) said data address stored in said first entry matches said first data address, and (ii) said LIB indication stored in said first entry is in said first state.
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Accused Products
Abstract
A load/store unit includes a buffer configured to retain store memory operations which have probed the data cache. Each entry in the buffer includes a last-in-buffer (LIB) indication which identifies whether or not the store in that entry is the youngest store in the buffer to update the memory locations specified by the corresponding store address. Load addresses are compared to the store addresses, and the comparison result is qualified with the corresponding LIB indication such that only the youngest store is identified as a hit. At most one load hit store is detected. In one embodiment, the buffer also stores loads which have probed the data cache. To associate the load with the youngest store which is older than the load, the buffer records the store instruction tag of a store which is hit by the load during the initial probe (according to the LIB indications during the initial probe). During reprobes, the LIB indications are ignored and instead the store instruction tags are compared to the recorded store instruction tag. As stores are inserted into the buffer, the store address is compared to the addresses in the buffer. If a hit is detected, the LIB indication for the hit store is set to a state indicating that the hit store in not the last in buffer to update the corresponding store address. The LIB indication for the newly inserted store is set to a last-in-buffer state.
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Citations
32 Claims
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1. A load/store unit comprising:
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a buffer including a plurality of entries, each of said plurality of entries configured to store a data address and a last-in-buffer (LIB) indication, wherein said LIB indication, in a first state, is indicative that a corresponding store memory operation is a youngest store memory operation within said buffer to update a memory location identified by said data address; and
control logic coupled to said buffer and to receive a first data address probing a data cache, wherein said control logic is configured to identify a first entry of said plurality of entries for which;
(i) said data address stored in said first entry matches said first data address, and (ii) said LIB indication stored in said first entry is in said first state.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A processor comprising:
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a data cache configured to store data; and
a load/store unit coupled to said data cache, said load store unit including;
a buffer including a plurality of entries, each of said plurality of entries configured to store a data address and a last-in-buffer (LIB) indication, wherein said LIB indication, in a first state, is indicative that a corresponding store memory operation is a youngest store memory operation within said buffer to update a memory location identified by said data address; and
control logic coupled to said buffer and to receive a first data address probing said data cache, wherein said control logic is configured to identify a first entry of said plurality of entries for which;
(i) said data address stored in said first entry matches said first data address, and (ii) said LIB indication stored in said first entry is in said first state.- View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A computer system comprising:
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a processor including;
a data cache configured to store data; and
a load/store unit coupled to said data cache, said load store unit including;
a buffer including a plurality of entries, each of said plurality of entries configured to store a data address and a last-in-buffer (LIB) indication, wherein said LIB indication, in a first state, is indicative that a corresponding store memory operation is a youngest store memory operation within said buffer to update a memory location identified by said data address; and
control logic coupled to said buffer and to receive a first data address probing said data cache, wherein said control logic is configured to identify a first entry of said plurality of entries for which;
(i) said data address stored in said first entry matches said first data address, and (ii) said LIB indication stored in said first entry is in said first state; and
an I/O device coupled to said processor, said I/O device configured to communicate between said computer system and another computer system to which said I/O device is coupled. - View Dependent Claims (24, 25)
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26. A method comprising:
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probing a data cache with a first data address corresponding to a first memory operation; and
identifying a first entry within a buffer of memory operations, said first entry storing a second data address of a second memory operation and a last-in-buffer (LIB) indication, said identifying including;
determining that said second address matches said first address; and
determining that said LIB indication is in a first state indicative that said second memory operation comprises a store memory operation which is youngest in said buffer to update a memory location identified by said second address. - View Dependent Claims (27, 28, 29, 30, 31, 32)
determining if store data within said first entry is valid; and
forwarding said store data as a result of said load memory operation.
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28. The method as recited in claim 27 further comprising, if said store data is invalid:
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selecting a store instruction tag from said first entry; and
storing said instruction tag in a second entry within said buffer, said second entry allocated to said load memory operation.
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29. The method as recited in claim 28 further comprising:
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selecting said load from said second entry to reprobe said data cache; and
comparing said store instruction tag in said second entry to a plurality of instruction tags in said buffer.
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30. The method as recited in claim 29 further comprising, if said store instruction tag matches said store instruction tag in said first entry, forwarding said store data from said first entry as a result of said load memory operation even if said LIB indication in said first entry is in a second state indicative that said store memory operation is not youngest within said buffer to update said memory location identified by said first data address.
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31. The method as recited in claim 26 further comprising, if said first memory operation comprises a second store memory operation, setting said LIB indication in said first entry to a second state indicative that said store memory operation is not youngest within said buffer to update said memory location identified by said first data address.
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32. The method as recited in claim 31 further comprising setting a second LIB indication in a second entry allocated to said second store memory operation to said first state.
Specification