Apparatus and method for communication between integrated circuit connected to each other by a single line

• US 6,393,576 B1
• Filed: 09/29/1997
• Issued: 05/21/2002
• Est. Priority Date: 11/09/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Burns, Christopher, Gates, Stillman F.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/938,828
• Time in Patent Office: 1,695 Days
• Field of Search: 395/281-286, 395/830, 395/306, 395/651, 395/200.31, 395/200.38, 395/200.66, 395/200.78, 395/800.32, 395/800.38, 709/201, 709/208, 709/236, 709/248, 710/101-106, 710/126, 712/32, 712/38, 713/1, 713/600
• US Class Current: 713/600
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Claims

1. A method for serially transferring information on a serial port input-output line between a first integrated circuit and a second integrated circuit, said method comprising:

transmitting an initialization signal on said serial port input-output line from said second integrated circuit to said first integrated circuit in response to a power-on reset signal;

only transmitting a signal from the first integrated circuit over the serial port input-output line to the second integrated circuit after receiving the initialization signal at the first integrated circuit;

driving a signal on said serial port input-output line by said second integrated circuit, subsequent to said initialization signal, only in response to a signal from said first integrated circuit on said serial port input-output line;

wherein the first integrated circuit comprises a master integrated circuit and the second integrated circuit comprises a slave integrated circuit.

2. The method of claim 1 wherein said second integrated circuit drives an acknowledge signal on said serial port input-output line within a predetermined time of receiving said signal from said first integrated circuit.

3. The method of claim 2 further comprising waiting by said first integrated circuit for completion of said acknowledge signal from said second integrated circuit before driving another signal on said serial port input-output line by said first integrated circuit.

4. The method of claim 1, wherein the initialization signal comprises at least one packet.

5. The method of claim 1, wherein the initialization signal comprises a device identification code.

6. An apparatus comprising:

a first integrated circuit having a first serial port, said first serial port having a first bidirectional pin;

a second integrated circuit having a second serial port, said second serial port having a second bidirectional pin;

a serial port input-output line connecting said first bidirectional pin to said second bidirectional pin, said serial port input-output line being a bidirectional line;

the second integrated circuit transmitting an initialization signal on said serial port input-output line to the first integrated circuit in response to a power-on reset signal;

the first integrated circuit only transmitting a signal over the bidirectional line to the second integrated circuit after receiving the initialization signal from the second integrated circuit;

the second integrated circuit driving a signal on said serial port input-output line, subsequent to said initialization signal, only in response to a signal from said first integrated circuit on said serial port input-output line;

wherein the first integrated circuit comprises a master integrated circuit and the second integrated circuit comprises a slave integrated circuit.

7. The apparatus of claim 6 wherein:

said first integrated circuit generates a buffered clock signal in response of a signal on said first clock pin;

said first integrated circuit contains a first plurality of internal modules;

said second integrated circuit contains a second plurality of internal modules;

said first integrated circuit provides said buffered clock signal to all internal modules contained therein; and

internal modules within said first and second integrated circuits operate synchronously with each other.

8. The apparatus of claim 6 wherein:

said second integrated claim circuit generates a second signl on said second bi-directional pin in response to a first signal from said first integrated circuit on said bi-directional pin; and

one of said first and second integrated circuits waits for a signal from the other of said first and second integrated circuits.

9. The apparatus of claim 6 wherein:

on power up said first circuit waits for an initialization signal on said serial port input-output line from said second integrated circuit, and

after transfer of said initialization signal said second integrated circuit tramits a signal on said serial port input-output line only in response to receipt of another signal transmitted on said serial port input-ouput line by said first integrated circuit.

10. The apparatus of claim 9 wherein:

the initialization signal comprise at least one packet.

11. The apparatus of claim 9 wherein:

the initialization signal comprises a device identification code.

12. The apparatus of claim 6 wherein said first serial port futher comprises:

a line controller circuit coupled to said first bi-directional pin;

wherein said line controll circuit transfers a packet serially to said first bi-directional pin; and

further wherein said line controller circuit and said acknowledge packet serially from said first bi-directional pin.

13. The apparatus of claim 6,

wherein said first circuit and said second integrated circuit communicate with each other only via said serial port input-output line.