Method and apparatus for diagnosing and conveying an identification code in post on a non-booting personal computer

• US 6,393,586 B1
• Filed: 02/04/1999
• Issued: 05/21/2002
• Est. Priority Date: 02/04/1999
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Sullivan, Tim, Springer, David, Sloan, Jeff
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/245,148
• Time in Patent Office: 1,202 Days
• Field of Search: 714/25, 714/36, 714/55, 717/124, 713/1, 713/2, 709/222, 710/10, 710/104
• US Class Current: 714/25
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]

Abstract

Method and apparatus for conveniently diagnosing and conveying to a user the cause of a catastrophic failure during POST of a non-booting PC is described. In one embodiment, when an ID code identifying a POST procedure is written to port 80h, the ID code is also written to a POST code field in a non-volatile memory device. If the PC “hangs” prior to completion of POST, there will be a non-zero byte in the POST code field identifying which POST procedure resulted in the hang. Accordingly, if during boot-up of the PC, a non-zero byte is detected in the POST code field, the ID code will be beeped to the user to identify the POST procedure that caused the PC to hang. If POST completes successfully, the POST code field is set to zero and POST continues through the normal sequence. In an alternative embodiment, after the ID code identifying the next POST procedure to be performed has been written to port 80h and to the POST code field, a timeout value is added to a watchdog timer, at which point the POST procedure is initiated. If the watchdog timer times out, the PC will automatically re-boot. Upon re-boot, if the value stored in the POST code field is non-zero, the POST code field value will be beeped as a message to the user, as described above.

Claims

1. A method performed by a computer, the method comprising:

during boot up of the computer, writing an ID code identifying a power on self test (“

POST”

) procedure to a POST code field in a nonvolatile memory device of the computer;

initiating the POST procedure;

responsive to the POST procedure completing successfully, determining whether there is another POST procedure to be performed and, if not, writing a zero to the POST code field before completing boot up of the computer; and

responsive to the POST procedure completing successfully and a determination that there is another POST procedure to be performed, writing an ID code of a next POST procedure to be performed to the POST code field.

2. The method of claim 1 further comprising responsive to the POST procedure not completing successfully, rebooting the computer.

3. The method of claim 2 wherein the rebooting the computer comprises:

determining whether a value stored in the POST code field is zero;

if the value stored in the POST code field is not zero, outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible; and

if the value stored in the POST code field is zero, completing boot up of the computer.

4. The method of claim 1 further comprising:

prior to the initiating the POST procedure, setting a watchdog timer to a predetermined time;

subsequent to the initiating the POST procedure and prior to the determining whether there are any more POST procedures to be performed, determining whether the watchdog timer has timed out;

if the watchdog timer has timed out, rebooting the computer; and

if the watchdog timer has not timed out, turning off the watchdog timer.

5. The method of claim 4 wherein the rebooting the computer comprises:

determining whether a value stored in the POST code field is zero;

if the value stored in the POST code field is not zero, outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible; and

if the value stored in the POST code field is zero, completing boot up of the computer.

6. A method performed by a computer, the method comprising:

during a power on self test (“

POST”

) sequence of the computer, writing an ID code identifying a POST procedure to a POST code field in a nonvolatile memory device of the computer;

initiating the POST procedure identified by the ID code in the POST code field;

responsive to the POST procedure not completing successfully, rebooting the computer, the rebooting comprising;

determining whether a value stored in the POST code field is zero;

if the value stored in the POST code field is zero, completing boot up of the computer;

if the value stored in the POST code field is not zero, outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible; and

if completing boot up of the computer is not possible, awaiting remedial measures.

7. The method of claim 6 further comprising:

responsive to the POST procedure completing successfully, determining whether there is another POST procedure to be performed;

responsive to a determination that there is not another POST procedure to be performed, writing a zero to the POST code field before completing boot up of the computer; and

responsive to a determination that there is another POST procedure to be performed, writing an ID code of a next POST procedure to be performed to the POST code field.

8. The method of claim 6 further comprising:

prior to the initiating the POST procedure, setting a watchdog timer to a predetermined time;

subsequent to the initiating the POST procedure and prior to the determining whether there are any more POST procedures to be performed, determining whether the watchdog timer has timed out;

if the watchdog timer has timed out, rebooting the computer; and

if the watchdog timer has not timed out, turning off the watchdog timer.

9. A method performed by a computer, the method comprising:

during boot up of the computer, writing an ID code identifying a power on self test (“

POST”

) procedure to a POST code field in a nonvolatile memory device of the computer;

setting a watchdog timer to a predetermined time sufficient to complete the POST procedure;

initiating the POST procedure;

determining whether the watchdog timer has timed out;

if the watchdog timer has timed out, automatically rebooting the computer; and

if the watchdog timer has not timed out, turning off the watchdog timer.

10. The method of claim 9 further comprising, if the watchdog timer has not timed out, determining whether there is another POST procedure to be performed and, if not, writing a zero to the POST code field before completing boot up of the computer.

11. The method of claim 9 wherein the automatically rebooting the computer comprises:

determining whether a value stored in the POST code field is zero;

if the value stored in the POST code field is not zero, outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible; and

if the value stored in the POST code field is zero, completing boot up of the computer.

12. The method of claim 9 further comprising:

responsive to the watchdog timer not timing out and a determination that there is another POST procedure to be performed, writing an ID code of a next POST procedure to be performed to the POST code field.

13. Apparatus comprising:

means for writing an ID code identifying a power on self test (“

POST”

) procedure to a POST code field in a nonvolatile memory device of the computer during boot up of the computer;

means for initiating the POST procedure;

means responsive to the POST procedure completing successfully for determining whether is another POST procedure to be performed and, if not, writing a zero to the POST code field before completing boot up of the computer; and

means responsive to the POST procedure completing successfully and a determination that there is another POST procedure to be performed for writing an ID code of a next POST procedure to be performed to the POST code field.

14. The apparatus of claim 13 further comprising means responsive to the POST procedure not completing successfully, rebooting the computer.

15. The apparatus of claim 14 wherein the means for rebooting the computer comprises:

means for determining whether a value stored in the POST code field is zero;

means for outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible, if the value stored in the POST code field is not zero; and

if the value stored in the POST code field is zero, completing boot up of the computer.

16. The apparatus of claim 13 further comprising:

means for setting a watchdog timer to a predetermined time prior to the initiating the POST procedure;

means for determining whether the watchdog timer has timed out subsequent to the initiating the POST procedure and prior to the determining whether there are any more POST procedures to be performed;

means for rebooting the computer if the watchdog timer has timed out; and

means for turning off the watchdog timer if the watchdog timer has not timed out.

17. The apparatus of claim 16 wherein the means for rebooting the computer comprises:

means for determining whether a value stored in the POST code field is zero;

means for outputting the ID code stored in the POST code field to a speaker of the computer, writing a zero to the POST code field, and completing boot up of the computer, if possible, if the value stored in the POST code field is not zero; and

if the value stored in the POST code field is zero, completing boot up of the computer.