Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system

• US 6,393,590 B1
• Filed: 12/22/1998
• Issued: 05/21/2002
• Est. Priority Date: 12/22/1998
• Status: Expired due to Term

• Current Assignee: Complex Memory LLC (IPValuation Partners, LLC)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Baker, Brian, Wood, Barry Everett
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US09/218,361
• Time in Patent Office: 1,246 Days
• Field of Search: 710/58, 710/262, 710/266, 710/267, 710/104, 710/15, 710/18, 709/103, 709/233, 709/234, 714/4, 714/10, 714/12, 714/11, 714/55, 714/23, 714/22, 711/147, 712/35, 712/12, 712/244, 713/1, 713/2
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

The present invention relates to a method and apparatus for ensuring fault detection and system recovery in a multiprocessor computing system. This system comprises a multitude of processing element modules, input/output processor modules and shared memory modules. Each module within the system includes an identical period sanity timer capable to reset the module once a predetermined limit count is reached. If a global clear signal is not received from the operating system scheduler by all modules prior to the expiry of the sanity timers, a system-wide reset is effected. Each processing element module within the system further includes a watchdog timer capable to reset the module once a predetermined limit count is reached. If a process is not run by the operating system scheduler on the processing element before the expiry of the watchdog timer, effectively clearing the watchdog timer, the processing element is reset and removed from service.

Claims

1. A processing element for use in a multiprocessor computing system, said processing element including:

a processor block;

an input port for receiving instruction elements for execution by said processor block;

a watchdog timer in operative relationship with said processor block, said watchdog timer capable to cause said processor block to reset after a first predetermined time interval has elapsed from setting the watchdog timer in a first initial condition;

a sanity timer in operative relationship with said processor block, said sanity timer capable to cause said processor block to reset after a second predetermined time interval has elapsed from setting the sanity timer in a second initial condition;

said processor block being responsive to the presence of at least one predetermined executable instruction element to cause said watchdog timer to acquire the first initial condition;

said processing element being responsive to an external signal to cause said sanity timer to acquire the second initial condition.

2. The processing element as defined in claim 1, wherein said first and second time intervals have different durations.

3. The processing element as defined in claim 2, wherein said watchdog timer includes a counter.

4. The processing element as defined in claim 2, wherein said sanity timer includes a counter.

5. The processing element as defined in claim 1, wherein said at least one predetermined executable instruction is part of a scheduler of an operating system.

6. The processing element as defined in claim 1, wherein the external signal is generated in response to execution of a program element part of an operating system.

7. A multiprocessor computing system comprising:

a plurality of processing elements, each processing element including;

a. a processor block;

b. an input port for receiving instruction elements for execution by said processor block;

c. a watchdog timer in operative relationship with said processor block, said watchdog timer capable to cause said processor block to reset after a first predetermined time interval has elapsed from setting the watchdog timer in a first initial condition;

d. a sanity timer in operative relationship with said processor block, said sanity timer capable to cause said processor block to reset after a second predetermined time interval has elapsed from setting the sanity timer in a second initial condition;

e. said processor block being responsive to the presence of at least one predetermined executable instruction element to cause said watchdog timer to acquire the first initial condition;

f. said processing element being responsive to an external signal to cause said sanity timer to acquire the second initial condition.

8. The multiprocessor computing system as defined in claim 7, wherein said first and second time intervals have different durations.

9. The multiprocessor computing system as defined in claim 8, wherein said watchdog timer includes a counter.

10. The multiprocessor computing system as defined in claim 8, wherein said sanity timer includes a counter.

11. The multiprocessor computing system as defined in claim 7, wherein said at least one predetermined executable instruction is part of a scheduler of an operating system.

12. A multiprocessor computing system as defined an claim 7, wherein the external signal is generated in response to execution of a program element part of an operating system.

13. A computer readable storage medium including a program element for execution by a multiprocessor computer system to implement an operating system, the multiprocessor computer system including a plurality of processing elements, each processing element including a watchdog timer and a sanity timer, said operating system including:

a scheduler for scheduling execution of processes by the computer system, said scheduler including at least one executable instruction to cause resetting of the watchdog timer of one of the plurality of processing elements of the computer system;

a system audit process that when executed by one of the plurality of processing elements of the computer system causes generation of at least one signal to cause resetting of the sanity timer of each one of the plurality of processing elements of the computer system.

14. A processing element for use in a multiprocessor computing system, said processing element including:

processing means;

input means for receiving instruction elements for execution by said processing means;

a watchdog timer means in operative relationship with said processing means, said watchdog timer means capable to cause said processing means to reset after a first predetermined time interval has elapsed from setting the watchdog timer means in a first initial condition;

a sanity timer means in operatives relationship with said processing means, said sanity timer means capable to cause said processing means to reset after a second predetermined time interval has elapsed from setting the sanity timer means in a second initial condition;

said processing means being responsive to the presence of at least one predetermined executable instruction element to cause said watchdog timer means to acquire the first initial condition;

said processing element being responsive to an external signal to cause said sanity timer means to acquire the second initial condition.

15. A method for preventing a processing element of a multiprocessor computer system from being reset, said processing element comprising:

a processor block;

an input port for receiving instruction elements for execution by said processor block;

a watchdog timer in operative relationship with said processor block, said watchdog timer capable to cause said processor block to reset after a first predetermined time interval has elapsed from setting the watchdog timer in a first initial condition;

a sanity timer in operative relationship with said processor block, said sanity timer capable to cause said processor block to reset after a second predetermined time interval has elapsed from setting the sanity timer in a second initial condition;

said method comprising the steps of;

a. executing by said processor block at least one instruction that causes said watchdog timer to acquire the first initial condition, repeatedly at a rate selected to prevent the watchdog timer from resetting said processing element;

b. supplying an external signal to said processing element to cause said sanity timer to acquire the second initial condition, repeatedly at a rate selected to prevent the sanity timer from resetting said processing element.