Method for remotely testing microelectronic device over the internet

• US 6,393,591 B1
• Filed: 02/12/1999
• Issued: 05/21/2002
• Est. Priority Date: 02/12/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Edmondson, Walter H., Jenkins, Jesse H. IV
• Primary Examiner(s): Ton, David
• Application Number:
  US09/249,907
• Time in Patent Office: 1,194 Days
• Field of Search: 714/724, 714/727, 714/726, 714/736, 714/725, 702/119, 702/117, 707/9, 364/578
• US Class Current: 714/725
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2201/875 Monitoring of systems including the internet

Abstract

The Internet is used to test an integrated circuit chip that is provided with boundary scan circuitry and plugged into a circuit board at a customer'"'"'s location. A host computer at the manufacturer'"'"'s location runs a web page server having the ability to remotely test a customer'"'"'s chip. The process is initiated by the customer connecting the circuit board to his own computer and logging onto the web site. The customer transmits customer identification and other data to the web server, which then transmits a downloader program and a JAVA program script to the customer'"'"'s computer. The customer'"'"'s computer then uses the downloader program to transmit high and low level device data describing the functionality of the chip to the host computer, which then generates and transmits a set of suitable test vectors to the customer'"'"'s computer. Then, the customer'"'"'s computer tests the chip using the boundary scan circuitry and test vectors and transmits the test results to the host computer, which then produces and transmits an evaluation of the results to the customer'"'"'s computer.

Claims

1. A method for testing a programmable logic device operatively coupled to a circuit board, the programmable logic device having boundary scan circuitry, the method comprising:

providing a first computer configured to communicate with the programmable logic device while operatively coupled to the circuit board, the first computer having access to design information for programming the programmable logic device;

putting the first computer in communication with a network;

sending the design information from the first computer over the network to a second computer in communication with the network, the second computer having access to a vector generator and a vector database;

the second computer, in response to receipt of the design information from the first computer;

accessing the vector database to obtain device vectors associated with the programmable logic device;

providing the device vectors and the design information to the vector generator; and

generating test vectors in response to the device vectors and the design information, the test vectors for testing the programmable logic device programmed according to the design information; and

communicating the test vectors to the first computer for testing the programmable logic device.

2. The method of claim 1 further comprising:

controlling the first computer with the second computer to, apply the test vectors to the boundary scan circuitry;

produce test data in partial response to application of the test vectors; and

communicate the test data to the second computer for analysis.

3. The method of claim 1 wherein the design information comprises design files and bitstream files, and the first computer or the second computer determines whether the bitstream files were generated from the design files without error.

4. The method of claim 1 wherein the first computer has access to a program configured to located at least a portion of the design information for providing to the second computer.

5. The method of claim 4 wherein the at least a portion of the design information is uploaded to a web page of a web page server associated with the second computer.

6. The method of claim 1 wherein the first computer has access to a script.

7. The method of claim 6 further comprising:

launching the script to control a programmer module;

testing the programmable logic device using the test vectors and the programmer module to access and influence the boundary scan circuitry; and

producing test results in response to the testing.

8. The method of claim 7 wherein the programmer module is a Joint Test Action Group (JTAG) programmer.

9. The method of claim 7 further comprising:

automatically communicating the test results to the second computer for evaluation.

10. The method of claim 9 further comprising:

evaluating the test results to generate an evaluation; and

communicating the evaluation to the first computer.

11. The method of claim 10 wherein the network comprises a portion of the Internet.

12. The method of claim 10 wherein the design information comprises device data.

13. The method of claim 10 wherein the first computer is configured to communicate with the programmable logic device while operatively coupled to the circuit board by use of a Joint Test Action Group (JTAG) cable.

14. The method of claim 10 wherein the design information comprises design source code files.

15. The method of claim 14 wherein the design source code files comprise a Boundary Scan Description Language (BSDL) file.

16. A method for testing a programmable logic device operatively coupled in situ to a circuit board, the programmable logic device having boundary scan circuitry, the method comprising:

providing a first computer configured to communicate with the programmable logic device while operatively coupled in situ to the circuit board, the first computer having access to device files, the device files comprising source code files and compiled versions of the source code files configured to program the programmable logic device;

putting the first computer in communication with a network;

providing a second computer in communication with the network, the second computer having access to a vector generator and a vector database, the second computer having access to a web page;

invoking the web page causing a program to be sent to the first computer, the program causing the first computer to send information to the second computer over the network, the information sent including the device files, software version data and client identification data;

in response to receipt of the information sent from the first computer, using the second computer to;

access the vector database to obtain vectors;

provide the vectors and the device files to the vector generator;

generate a set of test vectors with the vector generator in response to the vectors and the device files; and

communicate the set of test vectors, a script, and a programmer module to the first computer.

17. The method of claim 16 further comprising:

controlling the first computer with the second computer to;

launch the script to control the programmer module;

test the programmable logic device using the set of test vectors and the programmer module to access and influence the boundary scan circuitry;

produce test results in response to boundary scan testing of the programmable logic device; and

communicate the test results to the second computer for analysis.

18. The method of claim 17 further comprising:

evaluating the test results to generate an evaluation; and

communicating the evaluation from the second computer to the first computer.

19. The method of claim 16 wherein the source code files are written in a language for representing logic functions, and compiled versions of the source code files are in a bitstream form.

20. The method of claim 16 wherein the device files comprise a Boundary Scan Description Language (BSDL) file, and wherein the programmer module is a Joint Test Action Group (JTAG) programmer.