Method of a comprehensive sequential analysis of the yield losses of semiconductor wafers
First Claim
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1. A method for integrated yield management of semiconductor wafers being inspected for defects in a factory, comprising the steps of:
- defining and using a critical area analysis to predict yield impact of pattern disturbing defects;
defining and using spacial analysis to calculate the ratio of yield loss due to randomly distributed yield loss and regionally bound yield loss;
defining and using yield loss mode analysis to quantify the extent of yield loss being attributed to modes related to each type of spacial yield loss;
defining and using a yield loss manufacturing location to quantify yield loss during the manufacturing process for each yield loss mode;
defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to variations in nodes of in-line monitors; and
defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to node situational circumstances.
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Abstract
A method for improving yield management of semiconductors being inspected for defects. The method uses critical area analysis, spacial analysis, yield loss node analysis, yield loss manufacturing location, and yield loss cause analysis for both in-line monitors and at each node due to situational circumstances.
136 Citations
2 Claims
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1. A method for integrated yield management of semiconductor wafers being inspected for defects in a factory, comprising the steps of:
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defining and using a critical area analysis to predict yield impact of pattern disturbing defects;
defining and using spacial analysis to calculate the ratio of yield loss due to randomly distributed yield loss and regionally bound yield loss;
defining and using yield loss mode analysis to quantify the extent of yield loss being attributed to modes related to each type of spacial yield loss;
defining and using a yield loss manufacturing location to quantify yield loss during the manufacturing process for each yield loss mode;
defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to variations in nodes of in-line monitors; and
defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to node situational circumstances.
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2. An apparatus for integrated yield management of semiconductor wafers being inspected for defects in a factory, comprising:
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means for a critical area analysis to predict yield impact of pattern disturbing defects;
means for spacial analysis to calculate the ratio of yield loss due to randomly distributed yield loss and regionally bound yield loss;
means for yield loss mode analysis to quantify the extent of yield loss being attributed to modes related to each type of spacial yield loss;
means for a yield loss manufacturing location to quantify yield loss during the manufacturing process for each yield loss mode;
means for yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to variations in nodes of in-line monitors; and
means for yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to node situational circumstances.
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Specification
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsRoss, Ron, Atchison, Nick
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)GARBOWSKI, LEIGH M
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Application NumberUS09/333,717Time in Patent Office1,071 DaysField of Search716/1, 716/2, 716/4, 716/5, 716/19, 700/110, 700/121US Class Current716/56CPC Class CodesH01L 22/20 Sequence of activities cons...
