Microjoinery methods and devices

• US 6,393,685 B1
• Filed: 06/09/1998
• Issued: 05/28/2002
• Est. Priority Date: 06/10/1997
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Collins, Scott D.
• Primary Examiner(s): BUEKER, RICHARD R
• Application Number:
  US09/095,417
• Time in Patent Office: 1,449 Days
• Field of Search: 216/2,74,75,99,36 403/345 29/416,428,434 156/257
• US Class Current: 29/416
• CPC Class Codes: B81C 3/008 Aspects related to assembling from individually processed components, not covered by groups B81C3/001 - B81C3/002
• CPC Class Codes: Y10T 156/1064 Partial cutting [e.g., grooving or incising]
• CPC Class Codes: Y10T 29/49796 Coacting pieces
• CPC Class Codes: Y10T 29/49826 Assembling or joining
• CPC Class Codes: Y10T 29/4984 Retaining clearance for motion between assembled parts
• CPC Class Codes: Y10T 403/70 Interfitted members

Abstract

A wafer level interconnecting mechanism for assembling and packaging multiple MEMS devices (modules), using microfabricated, interlocking, mechanical joints to interconnect different modules and to create miniature devices. Various devices can be fabricated using these joints, including fiber-optic switches, xyz translational stages, push-n-lock locking mechanisms, slide-n-lock locking mechanisms, t-locking joints, fluidic interconnects, on/off valves, optical fiber couplers with xy adjustments, specimen holders, and membrane stops.

Claims

1. A method of fabricating a microjoint, comprising:

depositing and patterning an etch mask on a first (100) silicon wafer;

anisotropically etching said first (100) silicon wafer to a desired depth;

stripping said etch mask;

bonding said first (100) silicon wafer to a second wafer to form a wafer assembly;

thinning said first (100) silicon wafer to expose a microjoint element;

dicing said wafer assembly to form complementary mechanically interlocking microjoint elements; and

sliding said microjoint elements together until said microjoint elements interlock to form a microjoint that constrains movement between said microjoint elements.

2. A method as recited in claim 1:

wherein said microjoint is non-permanent.

3. A method as recited in claim 1, wherein said microjoint is modular.

4. A method as recited in claim 1, wherein said microjoint is non-permanent and modular.

5. A method as recited in claim 1, wherein said second wafer comprises a silicon wafer.

6. A method as recited in claim 5, wherein said second wafer comprises a (100) silicon wafer.

7. A method of fabricating a microjoint, comprising:

depositing and patterning an etch mask on a first silicon wafer;

anisotropically etching said first silicon wafer to a desired depth;

stripping said etch mask;

bonding said first silicon wafer to a second wafer to form a wafer assembly;

thinning said first silicon wafer to expose a microjoint element;

dicing said wafer assembly to form complementary mechanically interlocking microjoint elements; and

sliding said microjoint elements together until said microjoint elements interlock to form a microjoint that constrains movement between said microjoint elements.

8. A method as recited in claim 7:

wherein said microjoint is non-permanent.

9. A method as recited in claim 7, wherein said microjoint is modular.

10. A method as recited in claim 7, wherein said microjoint is non-permanent and modular.

11. A method as recited in claim 7, wherein said second wafer comprises a silicon wafer.

12. A method as recited in claim 11, wherein said wafers comprise (100) silicon wafers.