Semiconductor package and method for fabricating the same

• US 6,395,578 B1
• Filed: 05/19/2000
• Issued: 05/28/2002
• Est. Priority Date: 05/20/1999
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Shin, WonSun, Lee, SeonGoo, Chun, DoSung, Lee, SangHo, DiCaprio, Vincent
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LUU, CHUONG A
• Application Number:
  US09/574,541
• Time in Patent Office: 739 Days
• Field of Search: 438/615,617,613,612,127,26,64,55,123,112,124,126,106,107,121,113,108,118,110 257/710,697,787,700,783
• US Class Current: 438/106
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip

Abstract

Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with he ball lands by conductive via holes through the resin substrate, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be exposed therethrough, and a central through hole adapted to receive the semiconductor chip therein; electrical conductors that electrically connect the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate that covers the semiconductor chip, the electrical conductors, and at least part of the circuit board; and, a plurality of conductive balls fused on the ball lands of the circuit board, respectively.

Claims

1. A method for fabricating semiconductor packages, the method comprising:

providing a circuit board strip including a plurality of unit circuit boards, each unit circuit board having a plurality of first ball lands formed at a first major surface thereof, a plurality of bond fingers formed at an opposite second major surface thereof, vias through the circuit board each electrically connected between a bond finger and a first ball land, and a through hole between the first and second major surfaces;

receiving in each through hole a semiconductor chip having a first major surface, and an opposite second major surface provided with a plurality of input/output pads thereon, wherein the second major surface of the chip faces in the same direction as the first major surface of the respective circuit board;

electrically connecting the input/output pads of each semiconductor chip with associated ones of the bond fingers of the respective circuit board;

encapsulating the semiconductor chips, and filling the through hole of each unit circuit board of the circuit board strip using an encapsulating material;

fusing conductive balls on the first ball lands of each unit circuit board;

singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.

2. The method of claim 1, wherein the circuit board strip comprises:

a main strip including a resin substrate having a substantially rectangular strip shape, a first major surface and a second major surface;

a plurality of main slots extending to a desired length in a direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip;

a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards having one of the through holes;

a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the first ball lands;

a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and

cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be exposed therethrough.

3. The method of claim 1, wherein the circuit board strip comprises:

a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface;

a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards having one of the through holes;

a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the first ball lands;

a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and

cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be exposed therethrough.

4. The method of claim 1, further comprising attaching one or more closure members to the first surface of the substrate strip so that each through hole is covered thereby prior to receiving the semiconductor chip in the respective through hole.

5. The method of claim 2, further comprising:

attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that the closure members simultaneously cover associated ones of the through holes, prior to the step of receiving the semiconductor chips in the through holes.

6. The method according to claim 3, further comprising the step of:

attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that the closure members simultaneously cover associated ones of the through holes, prior to the step of receiving the semiconductor chips in the through holes.

7. The method according to claim 5, wherein attaching the closure member comprises:

preparing closure member strips each having closure members for an associated one of the sub-strips; and

individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.

8. The method according to claim 5, wherein attaching the closure member comprises:

preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots; and

attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.

9. The method of claim 4, wherein the one or more closure members are removed after encapsulating the semiconductor chips.

10. The method of claim 5, wherein the closure members are removed after encapsulating the semiconductor chips.

11. The method of claim 6, wherein the closure members are removed after encapsulating the semiconductor chips.

12. The method of claim 7, wherein the closure members are removed after encapsulating the semiconductor chips by inserting a bar into one or more of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.

13. The method of claim 8, wherein the closure members are removed after encapsulating the semiconductor chips by inserting a bar into one or more of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.

14. The method of to claim 4, wherein each closure member is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.

15. The method of claim 5, wherein each of the closure members is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.

16. The method of claim 6, wherein each of the closure members is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.

17. The method of claim 4, wherein a unitary body of encapsulant material covers the second major surface of all of the unit circuit boards of the circuit board strip.

18. The method according to claim 5, wherein a unitary body of encapsulant material covers the second major surface of all of the unit circuit boards of the circuit board strip.

19. The method according to claim 6, wherein a unitary body of encapsulant material covers the second major surface all of the unit circuit boards of the circuit board strip.

20. The method according to claim 17, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.

21. The method according to claim 18, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.

22. The method according to claim 19, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.

23. The method of claim 1, wherein encapsulating the circuit board strip comprises:

interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and

injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface.

24. The method of claim 2, wherein the encapsulating the circuit board strip comprises:

interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and

injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface.

25. The method of claim 4, wherein the encapsulating the circuit board strip comprises:

interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and

injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface, fills the through hole, and contacts the closure member.

26. The method of claim 9, wherein the encapsulating the circuit board strip comprises:

interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and

injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface, fills the through hole, and contacts the closure member.

27. The method of claim 1, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.

28. The method of claim 2, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.

29. The method of claim 3, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.

30. The method of claim 27, further comprising fusing a plurality of conductive balls on the second ball lands.

31. The method of claim 28, further comprising fusing a plurality of conductive balls on the second ball lands.

32. The method of claim 29, further comprising fusing a plurality of conductive balls on the second ball lands.

33. The method of claim 4, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.

34. The method of claim 33, wherein the one or more closure members are removed after encapsulating the semiconductor chips.

35. The method of claim 34, further comprising fusing a plurality of conductive balls on the second ball lands.