Method to improve copper process integration

• US 6,395,642 B1
• Filed: 12/28/1999
• Issued: 05/28/2002
• Est. Priority Date: 12/28/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Yu, Chen-Hua
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): CHEN, KIN CHAN
• Application Number:
  US09/473,032
• Time in Patent Office: 882 Days
• Field of Search: 438/703,710,712,720,722,687 134/95
• US Class Current: 438/720
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer

Abstract

A method is disclosed to improve copper process integration in the forming copper interconnects in integrated circuits. This is accomplished by integrating the process of forming a copper seed layer in an interconnect structure such as a trench or a groove, with the process of plasma cleaning of the structure prior to the electroplating of copper into the trench. NH₃ plasma can be used for this purpose. Or, H₂/N₂ thermal reduction can also be employed. The integrated process promotes well-controlled electro-chemical deposition (ECD) of copper for solid filling of the trench.

Claims

1. A method to improve copper process integration comprising the steps of:

providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;

forming an inter-level dielectric layer over said substrate;

patterning and etching said inter-level dielectric layer to form a damascene trench with inside walls therein;

performing physical or chemical vapor deposition of a diffusion barrier layer over said substrate including over said inside walls of said damascene trench;

forming a metal seed layer over said substrate including over said diffusion barrier layer;

performing oxide reduction over said metal seed layer, wherein said performing said oxide reduction on said seed layer is accomplished by using NH₃ plasma cleaning, or H₂/N₂ thermal reduction process;

forming a metal layer over said substrate including over said metal seed layer; and

removing excess metal layer from said substrate.

2. The method of claim 1, wherein said substrate is silicon.

3. The method of claim 1, wherein said inter-level dielectric layer comprises an oxide.

4. The method of claim 1, wherein said inter-level dielectric layer has a thickness between about 2000 to 10000 Å

.

5. The method of claim 1, wherein said damascene trench has a depth between about 2000 to 10000 Å

.

6. The method of claim 1, wherein said physical or chemical vapor deposition of diffusion barrier layer is accomplished with tantalum nitride or titanium nitride, or a ternary compound at a pressure between about 10 to 50 mtorr, temperature between about 20 to 300°

C.

7. The method of claim 1, wherein said diffusion barrier layer has a thickness between about 50 to 300 Å

.

8. The method of claim 1, wherein said forming a metal seed layer is accomplished by electro-chemical deposition of copper or by chemical vapor deposition of copper.

9. The method of claim 1, wherein said metal seed layer has a thickness between about 500 to 2000 Å

.

10. The method of claim 1, wherein said forming a metal layer is accomplished by depositing copper.

11. The method of claim 1, wherein said removing said excess metal is accomplished by chemical-mechanical polishing.

12. A method to improve copper process integration comprising the steps of:

providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;

forming an inter-level dielectric layer over said substrate;

forming a damascene structure in said inter-level dielectric layer;

forming a barrier layer in said damascene structure;

forming a copper seed layer over said barrier layer;

performing a copper oxide reduction over said copper seed layer, wherein said performing said copper oxide reduction on said copper seed layer is accomplished by using NH₃ plasma cleaning, or H₂/N₂ thermal reduction process;

forming a copper layer over said substrate including over said copper seed layer; and

removing excess copper layer from said substrate.

13. The method of claim 12, wherein said substrate is silicon.

14. The method of claim 12, wherein said inter-level dielectric layer comprises an oxide.

15. The method of claim 12, wherein said damascene structure has a depth between about 2000 to 10000 Å

.

16. The method of claim 12, wherein said barrier layer has a thickness between about 50 to 300 Å

.

17. The method of claim 12, wherein said copper seed layer has a thickness between about 500 to 2000 Å

.