Anisotropic wet etching
First Claim
1. A method for anisotropic wet etching, comprising the following steps:
- preparing a semiconductor substrate;
preparing an etching-resistant layer on said semiconductor substrate;
forming a pattern of intersecting lines to form a series of corners in said etch-resistant layer wherein said pattern comprises a series of masked and maskless areas wherein at least two sets of the masked lines intersect to surround and define a maskless area in a grid pattern at said corners, whereby the etching rate at the corner area of the substrate is moderated and said etching rate is relatively decided by the width of the masked lines;
etching said etch-resistant and semiconductor substrate layers in an etchant, and wherein the widths of the masked areas vary in a sequential manner in which the widths of a masked area in a first zone is 2 μ
m, in a second zone is 3 μ
m and in a third zone is 4 μ
m and the width of intervals is 5 μ
m.
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Abstract
A method for anisotropic wet etching is disclosed. In to this invention, a photo mask for the etching mask suited in the anisotropic wet etching is provided. In the photo mask, a pattern with a series of adjacent corners having a substantially rectangular, angle is formed. At the corner areas compensational patterns comprising masked grids are prepared. The pattern on the photo mask is then transferred to an etching mask of a semiconductor substrate such that a multi-level terrace structure with fine corners may be prepared during the etching of the substrate. The method of this invention is also applicable to semiconductor materials with the same diamond structure as that of silicon.
6 Citations
1 Claim
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1. A method for anisotropic wet etching, comprising the following steps:
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preparing a semiconductor substrate;
preparing an etching-resistant layer on said semiconductor substrate;
forming a pattern of intersecting lines to form a series of corners in said etch-resistant layer wherein said pattern comprises a series of masked and maskless areas wherein at least two sets of the masked lines intersect to surround and define a maskless area in a grid pattern at said corners, whereby the etching rate at the corner area of the substrate is moderated and said etching rate is relatively decided by the width of the masked lines;
etching said etch-resistant and semiconductor substrate layers in an etchant, and wherein the widths of the masked areas vary in a sequential manner in which the widths of a masked area in a first zone is 2 μ
m, in a second zone is 3 μ
m and in a third zone is 4 μ
m and the width of intervals is 5 μ
m.
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Specification
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- Resources
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Current AssigneeIndustrial Technology Research Institute
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Original AssigneeIndustrial Technology Research Institute
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InventorsLee, Chien-Chih, Wu, Ching-Yi, Chung, Chen-Kuei
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Primary Examiner(s)Utech, Benjamin L.
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Assistant Examiner(s)UMEZ ERONINI, LYNETTE T
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Application NumberUS09/137,446Time in Patent Office1,391 DaysField of Search438/745,753 216/41US Class Current438/745CPC Class CodesH01L 21/30608 Anisotropic liquid etching ...H01L 21/3083 characterised by their size...
