Trench MOS device and termination structure

• US 6,396,090 B1
• Filed: 09/22/2000
• Issued: 05/28/2002
• Est. Priority Date: 09/22/2000
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute, General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: Industrial Technology Research Institute, General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Kao, Ming-Che, Tsai, Ming-Jinn, Hsu, Chih-Wei, Kung, Pu-Ju, Liu, Chung-Min
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/668,663
• Time in Patent Office: 613 Days
• Field of Search: 257/242-244,513,520,397,332,329,510
• US Class Current: 257/242
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Claims

1. A termination structure for trench MOS devices, said termination structure comprising:

a semiconductor substrate having a plurality of trench MOS devices spaced from each other formed in an active region of said semiconductor substrate;

a trench termination formed from a boundary of said active region extended to an edge of said semiconductor substrate;

a MOS gate formed on a sidewall adjacent said boundary;

a termination structure oxide layer formed on said trench termination having a covering range from a portion of said MOS gate extended to said edge;

a first electrode formed on a backside surface of said semiconductor substrate; and

a second electrode formed atop said active region, an exposed portion of said MOS gate, and extended to cover a portion of said termination structure oxide layer.

2. The termination structure of claim 1, wherein said trench termination has a depth of between about 0.4-10 μ

m.

3. The termination structure of claim 1, wherein said MOS gate comprises a conductive layer and a gate oxide layer formed therebetween said trench termination and said conductive layer.

4. The termination structure of claim 1, wherein said trench MOS devices comprises power transistors.

5. The termination structure of claim 4, wherein said power transistors are devices selected from the group consisting of Schottky diodes, DMOSs, and IGBTs.

6. A termination structure for trench MOS devices, said termination structure and said trench MOS devices comprising:

a semiconductor substrate having a plurality of first trenches formed in an active region and a second trench formed adjacent said first trenches, said second trench being a trench termination;

a plurality of first MOS gates, respectively, formed in said first trenches, and a second MOS gate formed on a sidewall of said second trench;

a termination structure oxide layer formed in said second trench to cover a portion of said second MOS gate and to cover a bottom of said second trench; and

a first electrode formed on a backside surface of said semiconductor substrate; and

a second electrode formed atop said active region, an exposed portion of said MOS gate, and extended to cover a portion of said termination structure oxide layer.

7. The termination structure and trench MOS devices of claim 6, wherein said semiconductor substrate comprises a first layer and a base substrate, and said first layer has a first kind of conductive impurities lightly doped and said base substrate has said first kind of conductive impurities heavily doped, and thus said semiconductor substrate is for Schottky diode.

8. The termination structure and trench MOS devices of claim 7, wherein said first trenches and second trench are formed in said first layer having a depth of between about 0.4-10 μ

m.

9. The termination structure and trench MOS devices of claim 6, wherein said second trench is formed from a boundary of said active region to an edge of said semiconductor substrate, so that said second trench has one sidewall only.

10. The termination structure and trench MOS devices of claim 6, wherein gate material of said first gates and said second gate is selected from the group consisting of metal, polysilicon, and amorphous silicon.

11. The termination structure and trench MOS devices of claim 6, wherein said second electrode is to make a bending region of a depletion region distant from said boundary of said active region by at least 2 μ

m in distance.

12. The termination structure and trench MOS devices of claim 6, wherein said trench MOS devices are DMOS devices or IGBT devices.

13. A termination structure for trench MOS devices, said termination structure and trench MOS devices comprising:

a semiconductor substrate having a plurality of trench MOS devices spaced from each other formed in an active region of said semiconductor substrate;

a trench termination formed from a boundary of said active region extended to an edge of said semiconductor substrate;

a MOS gate formed on a sidewall adjacent said boundary;

a termination structure oxide layer formed on said trench termination having a covering range from a portion of said MOS gate extended to said edge; and

a conductive layer formed on a backside surface of said semiconductor substrate as a first electrode, and formed atop said active region, an exposed portion of said MOS gate and extended to cover a portion of said termination structure oxide layer, as a second electrode, so that a bending portion of said depletion region is distant from said boundary of said active region by at least 2 μ

m.

14. The termination structure and trench MOS devices of claim 13, wherein said semiconductor substrate comprises a first layer and a base substrate, and said first layer has a first kind of conductive impurities lightly doped and said base substrate has said first kind of conductive impurities heavily doped, and further said semiconductor substrate is for Schottky diode.

15. The termination structure and trench MOS devices of claim 13, wherein said trench termination has a depth of between about 0.4-10 μ

m.

16. The termination structure and trench MOS devices of claim 13, wherein said trench MOS devices and said MOS gate have a gate material selected from the group consisting of metal, polysilicon and amorphous silicon.

17. The termination structure and trench MOS devices of claim 13, wherein said trench MOS devices are power devices selected from the group consisting of Schottky diode, DMOS devices and IGBT devices.