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Field coupled power MOSFET bus architecture using trench technology

  • US 6,396,102 B1
  • Filed: 01/27/1998
  • Issued: 05/28/2002
  • Est. Priority Date: 01/27/1998
  • Status: Expired due to Term
First Claim
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1. A gate signal bus structure of a power MOS transistor comprising:

  • a.) an epitaxial layer of semiconductor material of first conductivity type having a surface and a plurality of trenches formed therein, wherein said plurality of trenches are spaced from one another so as to establish merged depletion regions of said epitaxial layer therebetween and around said trenches and extending substantially to said surface of said epitaxial layer without introducing a semiconductor material of second conductivity type into said epitaxial layer between the trenches so as to form said merged depletion regions;

    b.) a conductive material within each of said plurality of trenches; and

    c.) a thin layer of oxide layer within each of said plurality of trenches and spaced between said epitaxial layer and said conductive material.

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