Method of fabricating buried source to shrink chip size in memory array

• US 6,396,112 B2
• Filed: 02/20/2001
• Issued: 05/28/2002
• Est. Priority Date: 05/27/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsao, Jenn, Hsieh, Chia-Ta, Sung, Hung-Cheng, Kuo, Di-Son, Lin, Yai-Fen
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US09/784,824
• Publication Number:
  US 20010017387A1
• Time in Patent Office: 462 Days
• Field of Search: 257/374,302,305,296,301,314,315,316
• US Class Current: 257/394
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Claims

1. An integrated buried source line in a memory array comprising:

a substrate having active and field regions defined;

a buried trench formed in active region of said substrate;

said buried trench having an anti-punch-through oxide layer covering only partially the sidewalls below a lip depth from the mouth of said buried trench, and not the bottom of said buried trench; and

said buried trench having a buried source line integrated with the source region of said substrate.

2. The integrated source of claim 1, wherein said buried trench is formed with selective epitaxial growth (SEG) layer.

3. The integrated source of claim 1, wherein said buried trench has a depth between about 1500 to 4000 Å

.

4. The integrated source of claim 1, wherein said anti-punch-through sidewalls have a thickness between about 80 to 200 Å

.

5. The integrated source of claim 1, wherein said lip depth from said mouth of said buried trench is between about 100 to 250 Å

.