System and method for combining integrated circuit final test and marking

• US 6,396,295 B1
• Filed: 06/02/1998
• Issued: 05/28/2002
• Est. Priority Date: 06/02/1998
• Status: Expired due to Fees

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Inventors: Robinson, Donald E., Bandali, Mo
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US09/088,961
• Time in Patent Office: 1,456 Days
• Field of Search: 324/754,158.2 209/573
• US Class Current: 324/750.03
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12

Abstract

A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.

Claims

1. A system for testing and marking integrated circuits comprising:

an environmental station to stress the integrated circuits before testing;

a testing station for testing integrated circuits after being stressed in the environmental station, determining if the integrated circuits passed or failed, placing the integrated circuits in a pass bin if the integrated circuits passed, and placing the integrated circuits in a fail bin if the integrated circuits failed;

a cool-down station to allow the integrated circuits to cool before marking the integrated circuits; and

a marking station for marking identification information on the integrated circuits in the pass bin and for marking identification information on the integrated circuits in the fail bin that is different from the identification information marked on the integrated circuits in the pass bin.

2. A system for testing and marking integrated circuits comprising:

a testing station for testing integrated circuits, determining if the integrated circuits passed or failed, and placing the integrated circuits in a pass bin if the integrated circuits passed; and

a marking station for marking identification information on the integrated circuits in the pass bin;

wherein the marking station further comprises;

a detector to detect when an integrated circuit was received in the marking station,

a marker-stop to position the integrated circuit for marking,

a marker to mark the integrated circuit with the identification information, and

a controller, responsive to the detector, for activating the marker-stop to position the received integrated circuit for marking, causing the marker to mark the integrated circuit, and after marking, releasing the marker-stop to allow the marked integrated circuit to exit the marking station.

3. The system of claim 2 further comprising:

a sequencer-stop, wherein if the integrated circuits are in the marking station, the controller activates the sequencer-stop to prevent additional integrated circuits from entering the marking station.

4. The system of claim 2 further comprising:

a curing stop, wherein the controller activates the curing stop before releasing the marker-stop to allow the marked integrated circuits to dry for a predetermined dry-time.

5. The system of claim 2, further comprising

a cool-down station;

and

a conveyor to automatically move the integrated circuits from the cool-down station to the marking station.

6. The system of claim 5, wherein the conveyor comprises channels for supporting and automatically moving the integrated circuits, the pass bin and the fail bin, each having at least one channel,

the channels causing the integrated circuits to automatically move from the cool-down station to the marking station,

the cool-down station having a cool-down-stop to hold the integrated circuits within the channel for a predetermined cool-down time before allowing the integrated circuits to pass to the marking station.

7. The system of claim 2 wherein

a robot arm moves the integrated circuits from the testing station to the marking station.

8. A marking station for use with a testing station having bins that supply tested integrated circuits, including at least one pass bin for holding integrated circuits that passed the tests, comprising:

a detector to detect when an integrated circuit is received in the pass bin of the marking station;

a sequencer-stop to prevent integrated circuits from flowing into the marking station;

a marker to mark identification information on the integrated circuit in the pass bin;

a marker-stop to position the integrated circuit with respect to the marker for marking; and

a controller that, in response to the detector, determines that the integrated circuit is in the marking station, then the controller activates the sequencer-stop to prevent additional integrated circuits from entering the marking station, activates the marker-stop to position the received integrated circuit for marking, causes the marker to mark the integrated circuit, and releases the marker-stop to allow the marked integrated circuit to exit the marking station after being marked.

9. A system for testing and marking integrated circuits comprising:

a testing station for testing integrated circuits, determining if the integrated circuits passed or failed, and placing the integrated circuits in a pass bin if the integrated circuits passed; and

a marking station for marking identification information on the integrated circuits in the pass bin, including;

a detector to detect when an integrated circuit is received in the marking station;

a marker-stop to position the integrated circuit for marking; and

a marker to mark the integrated circuit with the identification information; and

a controller, responsive to the detector, for activating the marker-stop to position the received integrated circuit for marking, causing the marker to mark the integrated circuit, and after marking, releasing the marker-stop to allow the marked integrated circuit to exit the marking station,

wherein the marker-stop includes

a solenoid controlled by the controller;

a lever coupled to the solenoid, and

a pin attached to the lever, the pin being disposed with respect to the pass bin, such that the controller activates the solenoid to raise the pin so that the integrated circuit is stopped in the pass bin.

10. The system of claim 9,

wherein the testing station is configured to place the integrated circuits in a fail bin if the integrated circuits failed;

further including a second marking station for marking identification information on the integrated circuits in the fail bin, including;

a detector to detect when an integrated circuit is received in the marking station,

a marker-stop to position the integrated circuit for marking;

a marker to mark the integrated circuit with the identification information.