Semiconductor integrated circuit equipped with function for controlling the quantity of processing per unit time length by detecting internally arising delay

• US 6,396,321 B1
• Filed: 02/23/2000
• Issued: 05/28/2002
• Est. Priority Date: 02/24/1999
• Status: Expired due to Term

• Current Assignee: NEC Personal Computers, Ltd. (Lenovo Group Ltd.)
• Original Assignee: NEC Corporation
• Inventors: Watanabe, Masataka, Moriyama, Shuichi
• Primary Examiner(s): Tran, Toan
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US09/511,327
• Time in Patent Office: 825 Days
• Field of Search: 327/262,149,158,295,261
• US Class Current: 327/158
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

A semiconductor integrated circuit 10 comprises an internal logic circuit 16, a delay detecting circuit 11 which monitors changes in delay length within the semiconductor integrated circuit 10, and a central control circuit 14 which controls the quantity of processing per unit time length by the internal logic circuit 16 on the basis of changes in delay length monitored by the delay detecting circuit 11.

Claims

1. A semiconductor integrated circuit comprising:

an internal logic circuit;

a delay detecting circuit which detects changes in delay length of an internal signal within said semiconductor integrated circuit by comparing values of said internal signal at different times; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuit on the basis of said changes in delay length,

wherein said delay detecting circuit comprises a delay change rate detecting circuit which transmits a comparative result to said central control circuit, and

wherein said delay change rate detecting circuit comprises;

a first element which holds a first value in response to said internal signal at a first timing;

a second element which holds a second value in response to said internal signal at a second timing; and

a third element which generates said comparative result by comparing said first value and said second value.

2. The semiconductor integrated circuit as claimed in claim 1, wherein said changes in said delay length comprise increases in said delay length.

4. The semiconductor integrated circuit as claimed in claim 1, wherein said delay detecting circuit further comprises a programmable delay circuit which can change delay length arising in said programmable delay circuit in accordance with a direction of said central control circuit, and

wherein said internal signal comprises an output signal of said programmable delay circuit.

5. The semiconductor integrated circuit as claimed in claim 4, wherein said central control circuit, when said comparative result indicates no increase in delay occurred to said output signal of said programmable delay circuit, makes delay length arising in said programmable delay circuit greater than a present delay length.

7. The semiconductor integrated circuit as claimed in claim 4, wherein said programmable delay circuit comprises a plurality of delay circuits generating different delay lengths, and

wherein said central control circuit transmits a delay circuit selection signal to said delay detecting circuit for selecting one of said plurality of delay circuits.

8. The semiconductor integrated circuit as claimed in claim 7, wherein said central control circuit selects one of said plurality of delay circuits based on said comparative result.

12. The semiconductor integrated circuit as claimed in claim 1, wherein said delay detecting circuit transmits an alarm signal to said central control circuit to indicate that a delay length is nearing a maximum limit.

3. A semiconductor integrated circuit comprising:

an internal logic circuit;

a delay detecting circuit which detects changes in delay length of an internal signal within said semiconductor integrated circuit; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuit on the basis of changes in delay length monitored by said delay detecting circuit,

wherein said delay detecting circuit comprises a delay change rate detecting circuit which transmits a comparative result comparing a value of said internal signal of said semiconductor integrated circuit at first time and a value of the signal at second time after predetermined time elapse from the first time, to said central control circuit,

wherein said comparative result indicates whether or not an increase in delay occurred to said internal signal, and

wherein said delay change rate detecting circuit comprises;

a first element which holds a first value in response to said internal signal at a first timing;

a second element which holds a second value in response to said internal signal at a second timing; and

a third element which generates said comparative result by comparing said first value and said second value.

6. A semiconductor integrated circuit comprising:

plurality of internal logic circuits;

plurality of delay detecting circuits, each of which is laid out in the vicinity of one or another of the internal logic circuits, and monitors changes in delay length of an internal signal within said semiconductor integrated circuit; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuits on the basis of changes in delay length monitored by said delay detecting circuits,

wherein each delay detecting circuit comprises a delay change rate detecting circuit which transmits a comparative result to said central control circuit, and

wherein said delay change rate detecting circuit comprises;

a first element which holds a first value in response to said internal signal at a first timing;

a second element which holds a second value in response to said internal signal at a second timing; and

a third element which generates said comparative result by comparing said first value and said second value.

9. A semiconductor integrated circuit comprising:

an internal logic circuit;

a delay detecting circuit which detects changes in delay length of an internal signal within said semiconductor integrated circuit by comparing values of said internal signal at different times; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuit on the basis of said changes in delay length,

wherein said central control circuit controls a quantity of processing by instructing said internal logic circuit to put off processing.

10. A semiconductor integrated circuit comprising:

an internal logic circuit;

a delay detecting circuit which detects changes in delay length of an internal signal within said semiconductor integrated circuit by comparing values of said internal signal at different times; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuit on the basis of said changes in delay length,

wherein said central control circuit controls a quantity of processing by temporarily suspending a supply of a clock signal to said internal logic circuit.

11. A semiconductor integrated circuit comprising:

an internal logic circuit;

a delay detecting circuit which detects changes in delay length of an internal signal within said semiconductor integrated circuit by comparing values of said internal signal at different times; and

a central control circuit which controls the quantity of processing per unit time length by said internal logic circuit on the basis of said changes in delay length,

wherein said central control circuit controls a quantity of processing by reducing a frequency of a clock signal to said internal logic circuit.