Method and apparatus for receiving high speed signals with low latency

• US 6,396,329 B1
• Filed: 01/06/2000
• Issued: 05/28/2002
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/478,914
• Time in Patent Office: 873 Days
• Field of Search: 327/51,52,55,57,65,69,70,336,344,208,319,333 365/189.05,189.07,207 326/30,82,86,90
• US Class Current: 327/336
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/028 : Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 : Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 : Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Claims

1. A bus receiver comprising:

an integrator to accumulate charge in accordance with an input signal during an integration time interval defined by a start integration timing event and an end integration timing event to produce an output voltage; and

a sense amplifier to sample and convert the output voltage from the integrator into a logic signal representing a state of the input signal in response to a sensing timing event that is substantially concurrent with the end integration timing event.

2. The bus receiver of claim 1 wherein the integrator includes integration nodes to accumulate charge by charging and discharging respective ones of the integration nodes in accordance with the input signal.

3. The bus receiver of claim 1 wherein the integrator comprises:

a plurality of current steering blocks; and

a plurality of capacitive elements coupled to the current steering blocks, each capacitive element having integration nodes to accumulate charge, wherein during the integration time interval, at least one of the current steering blocks adjusts a charge on at least one integration node in accordance with the input signal to generate the output voltage.

4. The bus receiver of claim 1 wherein the integrator comprises:

a first current steering block;

a second current steering block; and

first and second capacitive elements, having integration nodes, coupled between the first and the second current steering blocks, such that during the integration time interval the first and the second current steering blocks adjust a charge on at least one integration node in accordance with the input signal to generate the output voltage.

5. The bus receiver of claim 4 further comprising:

a first current source, coupled to the first current steering block, to provide a first current; and

a second current source, coupled to the second current steering block, to provide a second current,

such that during the integration time interval the first and the second current steering blocks adjust the charge across the capacitive elements in accordance with the first current and the second current.

6. The bus receiver of claim 5 wherein the first current is substantially the same as the second current.

7. The bus receiver of claim 3 wherein the input signal has a low voltage and a high voltage, wherein at least one of the current steering blocks adjusts the charge of at least one integration node when the input signal has a common mode voltage that falls between the low voltage and the high voltage.

8. The bus receiver of claim 1 wherein a first edge of a clock signal defines the start integration timing event and a second edge of the clock signal defines the end integration timing event, wherein the second clock signal edge activates the sense amplifier to sample and convert the output voltage from the integrator into the logic signal.

9. The bus receiver of claim 1, wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, and a time between the start integration timing event and the end integration timing event is less than or equal to one-half of the system clock period.

10. The bus receiver of claim 1, wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, further comprising:

a latch to store the logic signal from the sense amplifier such that an output interval defined by the sensing timing event to a time when the latch outputs the stored logic signal is less than or equal to one half-cycle of the system clock period.

11. The bus receiver of claim 10 wherein a time from the start integration timing event to when the latch outputs the stored logic signal is less than the system clock period.

12. The bus receiver of claim 1 wherein the integrator integrates a predetermined amount of current in accordance with a polarity of the input signal to produce the output voltage.

13. The bus receiver of claim 1 wherein the input signal is a differential signal and the integrator integrates a predetermined amount of current in accordance with a polarity of the voltage difference of the differential input signal to produce the output voltage.

14. The bus receiver of claim 1 wherein the integrator integrates a predetermined amount of current in accordance with a polarity of the input signal with respect to a reference voltage to produce the output voltage.

15. The bus receiver of claim 1 further comprising:

a preamplifier to receive an unconditioned input signal, and conditions the unconditioned input signal to generate the input signal.

16. The bus receiver of claim 1 further comprising:

a preamplifier to receive an unconditioned input signal, conditions the unconditioned input signal to provide the input signal to the integrator, wherein the input signal includes two pairs of differential conditioned signals,

wherein the integrator accumulates the charge in accordance with the polarity of the two pairs of differential conditioned signals, wherein the output voltage includes two pairs of differential integrated signals, and

the sense amplifier determines the logic signal representing the state of the input signal in accordance with the two pairs of differential integrated signals.

17. The bus receiver of claim 1 wherein the output voltage of the integrator includes two pairs of differential integrated signals, and the sense amplifier receives the two pairs of differential integrated signals and determines the logic signal representing the state of the input signal in accordance with the two pairs of differential integrated signals.

18. The bus receiver of claim 2 further comprising:

a precharge circuit to precharge the integration nodes to a predetermined charge.

19. The bus receiver system of claim 1 wherein the integrator accumulates the output voltage on one or more pairs of integration nodes, further comprising:

a compensation circuit to provide a predetermined amount of charge to at least one integration node sufficient to compensate for parasitic capacitance between the integration nodes.

20. The bus receiver of claim 1, wherein the integrator accumulates the output voltage on integration nodes, the input signal includes a first bit and a second bit, the first bit being received during a first bit time, the second bit being received during a second bit time, the second bit time being after the first bit time, the integrator accumulates a first output voltage for the first bit on the integration nodes during the first bit time, further comprising:

an equalization circuit to adjust an initial charge on the integration nodes based on the first output voltage prior to the second bit time to compensate for inter-symbol interference between the first bit and the second bit.

21. The bus receiver of claim 1, wherein the integrator accumulates the output voltage on integration nodes, further comprising:

a voltage offset cancellation circuit coupled to the integration nodes to alter a precharge voltage at the integration nodes.

22. The bus receiver of claim 1 wherein the integrator operates synchronously with respect to a system clock having a first edge and a second edge, and further comprising:

a timing adjustment circuit to delay the start integration timing event with respect to the first edge of the system clock, and the sensing timing event is synchronous with the second edge of the system clock.

23. An integrating receiver comprising:

a preamplifier to receive an unconditioned input signal, condition the unconditioned input signal to provide a conditioned input signal to the integrator, wherein the input signal includes two pairs of differential conditioned signals; and

a sense amplifier including capacitive elements having integration nodes to accumulate charge in accordance with the input signal during an integration time interval defined by a start integration timing event and an end integration timing event to produce an integration voltage, and to sample and convert the integration voltage into a logic signal representing a state of the input signal in response to a sensing timing event that is substantially concurrent with the end integration timing event.

24. The integrating receiver of claim 23 further comprising:

a precharge circuit to precharge the integration nodes to a predetermined charge.

25. A memory comprising:

a plurality of bus receivers outputting a plurality of logic signals, each receiver including;

an integrator to accumulate charge to produce an output voltage in accordance with an input signal during an integration time interval defined by a start integration timing event and an end integration timing event;

a sense amplifier to sample and convert the output voltage from the integrator into one of the logic signals that represents a state of the input signal in response to a sensing timing event substantially concurrent with the end integration timing event; and

a plurality of memory cells to store signals representing a state of the plurality of logic signals.

26. The memory of claim 25 wherein a clock signal defines the start integration timing event and end integration timing event with clock signal edges, wherein the same clock signal edge that ends the integration time interval activates the sense amplifier to sample and convert the output voltage from the integrator into a logic signal.

27. The memory of claim 25, wherein the start integration timing event and the end integration timing event are based on a system clock having a system clock period, and a time between the start integration timing event and the end integration timing even is less than or equal to one-half of the system clock period, further comprising:

a latch to store the logic signal from the sense amplifier in response to the sensing timing event, such that an output interval defined by the sensing timing event to a time when the latch outputs the stored logic signal is less than one half-cycle of the system clock period, wherein each memory cell receives the logic signal from the latch.

28. The memory of claim 25 further comprising:

a preamplifier coupled to receive the input signal, the preamplifier providing a conditioned input signal.

29. A memory comprising:

a plurality of bus receivers outputting a plurality of logic signals, each receiver including;

a preamplifier for receiving an external data signal, the preamplifier providing an input signal on a first pair of outputs and a second pair of outputs;

the input signal having an associated polarity;

an inverter having an input for receiving a precharge signal, the inverter inverting the precharge signal to provide a first control signal having a first predetermined voltage and a second control signal having a second predetermined voltage;

a sense amplifier including;

a first pair of pass transistors connected between the first pair of outputs of the preamplifier and a first pair of integration nodes, the first pair of pass transistors each having a control input receiving the first control signal;

a second pair of pass transistors connected between the second pair of outputs of the preamplifier and a second pair of integration nodes, the second pair of pass transistors each having a control input receiving the second control signal;

a first capacitive element coupled between a pair of integration nodes;

a second capacitive element coupled between another pair of integration nodes;

wherein a transition of the precharge signal starts an integration interval during which voltage is accumulated on the integration nodes,

the sense amplifier converts the voltage at the integration nodes into a logic signal during a sensing interval in response to a transition of a sense signal, the logic signal representing the polarity of the input signal, and

the receiver system provides the logic signal after the transitions of the precharge signal and sense signals; and

a plurality of memory cells store the plurality of logic signals.

30. A multiple receiver system comprising:

a first and a second receiver to receive an input signal including a first input bit and a second input bit, the first receiver receiving the first input bit during a first bit time, the second receiver receiving the second input bit during a second bit time;

each receiver comprising;

an integrator to receive the input signal, the integrator to accumulate, during an integration time interval, charge to provide an output voltage across a first and a second integration node in accordance with the input signal, a first timing event starting the integration time interval, the first and second integration nodes being precharged prior to the first timing event; and

a sense amplifier coupled to receive the output voltage from the integrator, the sense amplifier to sample the output voltage from the integrator following the first timing event and convert the sampled voltage into a logic signal in response to a second timing event, the logic signal representing a polarity of the input signal;

a first equalization circuit, coupled between the first integration node of the first receiver and the second integration node of the second receiver, the first equalization circuit to receive a control voltage to set a precharge voltage of the first integration node of the first receiver in accordance with the output voltage on the second integration node of the second receiver; and

a second equalization circuit, coupled between the second integration node of the second receiver and the first integration node of the first receiver, the second equalization circuit to receive the control voltage to set a precharge voltage of the second integration node of the second receiver in accordance with the output voltage on the first integration node of the first receiver.

31. The multiple receiver system of claim 30, further comprising a latch for storing the logic signal of the sense amplifier.

32. The multiple receiver system of claim 30, further comprising:

a voltage offset compensation circuit connected to each of the integration nodes of the first receiver and the second receiver, the voltage offset compensation circuitry receiving an adjustment signal to alter the precharge voltage of each of the integration nodes.

33. A method of receiving an input signal in a high-speed signaling system, the method comprising:

accumulating a charge on integration nodes during an integration time interval based on the input signal to produce an integration voltage, a first timing event starting the integration time interval;

sampling the integration voltage to provide a sampled voltage following the first timing event; and

converting the sampled voltage into a logic signal during a sensing interval, a second timing event starting the sensing interval and the logic signal representing a polarity of the external data input signal,

wherein the second timing event occurs after the first timing event, and the logic signal is available after the occurrence of the second timing event.

34. The method of claim 33, further comprising storing the logic signal.

35. The method of claim 33, further comprising preamplifying an unconditioned input signal to provide the input signal.

36. A receiver system comprising:

means for conditioning an input signal to provide a conditioned signal;

means for accumulating charge, during a first time interval, to provide a differential voltage in accordance with the conditioned signal;

means for sampling the differential voltage to provide a sampled voltage; and

means for converting the sampled voltage into a logic signal during a second time interval, the logic signal representing a state of the input signal;

wherein the second timing interval begins after the first time interval begins.

37. A bus receiver comprising:

means for accumulating charge to provide an output voltage based on an input signal during an integration time interval defined by a start integration timing event and an end integration timing event; and

means for sampling and converting the output voltage from the integrator into a logic signal representing a state of the input signal in response to a sensing timing event that is substantially concurrent with the end integration timing event.

38. The bus receiver of claim 37 wherein the integrator comprises:

first means for steering current;

second means for steering current; and

means for storing the charge on integration nodes, coupled between the first and the first means for steering current, such that during the integration time interval the first and the second means for steering current adjusts the charge on at least one integration node in accordance with the input signal.

39. The bus receiver of claim 38 wherein the first means for steering current and the second means for steering current are coupled to a first current source and a second current source, respectively, such that during the integration time interval the first and the second means for steering current adjust the charge on at least one integration node using current from the first current source and the second current source.

40. The bus receiver of claim 37 wherein a clock signal defines the start integration timing event and end integration timing event with clock signal edges, wherein the same clock signal edge that ends the integration time interval activates the means for sampling and converting the output voltage from the integrator into a logic signal.

41. The bus receiver of claim 37, wherein the start integration timing event and the end integration timing event are based on a system clock having a system clock period, and a time between the start integration timing event and the end integration timing even is less than or equal to one-half of the system clock period, further comprising:

means for storing the logic signal from the means for sensing and converting such that an output interval defined by the sensing timing event to a time when the means for storing the logic signal outputs the stored logic signal is less than one half-cycle of the system clock period.

42. The bus receiver of claim 37 further comprising:

means for conditioning an unconditioned input signal input signal, and generating the data input signal by conditioning the unconditioned input signal.