Class E Doherty amplifier topology for high efficiency signal transmitters

• US 6,396,341 B1
• Filed: 12/29/2000
• Issued: 05/28/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Pehlke, David R.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/752,625
• Time in Patent Office: 515 Days
• Field of Search: 330/10,136,207 A,251
• US Class Current: 330/10
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 3/2176 Class E amplifiers

Abstract

A Doherty amplifier circuit is provided comprising a digital signal processor for producing separated amplitude and phase modulated waveforms, and a plurality of class E amplifiers in communication with the digital signal processor. Each of the amplifiers has an input for receiving signals corresponding to the waveforms, and outputs linked to a shared load network. In this way, a scheme for efficient amplification of amplitude modulated waveforms is achieved across a wide dynamic range and for a large peak-to-average ratio using only input modulated techniques.

Claims

1. An amplifier circuit comprising:

a digital signal processor for producing separated amplitude and phase modulated waveforms; and

a plurality of class E amplifiers in communication with said digital signal processor, each of said amplifiers having an input for receiving signals corresponding to said waveforms, and outputs linked to a shared load network.

2. The amplifier circuit of claim 1 wherein said circuit is configured to allow one of said amplifiers to saturate prior to saturation of others of said amplifiers.

3. The amplifier circuit of claim 1 wherein at least two of said amplifiers have different output power ratings.

4. The amplifier circuit of claim 1 wherein said plurality of class E amplifiers further comprises a first and a second amplifier, said first amplifier functioning as a carrier amplifier receiving a first amplitude-modulated baseband signal from said digital signal processor, said second amplifier receiving a second amplitude-modulated baseband signal from said digital signal processor.

5. The amplifier circuit of claim 1 wherein each of said class E amplifiers is configured to utilize an envelope signal to adjust its individual output power level.

6. The amplifier circuit of claim 2 further comprising a plurality of digital to analog converters in communication with said digital signal processor, said converters for converting said signals to high-resolution analog signals for input to said amplifiers.

7. The amplifier circuit of claim 2 further comprising at least one modulating upconverter linked to said digital signal processor for modulating said waveforms.

8. The amplifier circuit of claim 5 further comprising at least one bandpass noise filter linked to said upconverter.

9. The amplifier circuit of claim 6 further comprising an impedance adjusting element linked to said peaking amplifier.

10. The circuit of claim 5 further comprising:

a control device for at least one of said amplifiers for receiving amplitude information or phase information from a primary waveform, and

a plurality of switching devices in communication with said control device and said at least one amplifier, said switching devices each having a different current resistance;

wherein said control device uses said information to select an active switching device to create a secondary waveform for input to the matching network of said at least one amplifier.

11. The circuit of claim 10 wherein said switching devices are transistors each having a gate, and said control device controls said switching devices by providing said information at the gate of said switching device.

12. The circuit of claim 1 further comprising:

a feedback loop for sensing VSWR reflection from an antenna in communication with one of said amplifiers, said feedback loop in communication with said digital signal processor;

wherein said digital signal processor adjusts said waveforms to correct for said VSWR reflection.

14. The amplifier circuit of claim 12 further comprising at least one modulating upconverter linked to said digital signal processor for modulating said RF signal.

15. The amplifier circuit of claim 14 further comprising at least one bandpass noise filter linked to said upconverter.

13. An amplifier circuit comprising:

a digital signal processor producing a plurality of digital amplitude modulation signals and at least one digital phase modulated signal;

a plurality of digital to analog converters in communication with said digital signal processor for converting said digital amplitude modulation signals into analog amplitude modulation signals, and for converting said digital phase modulated signal into an analog phase modulated signal;

a plurality of class E amplifiers in communication with said digital to analog converters to receive said analog signals, at least one of said amplifiers functioning as a carrier amplifier connected to receive said analog phase modulated signal and one of said analog amplitude modulation signals, and at least another of said amplifiers functioning as a peaking amplifier connected to receive said analog phase modulated signal and another of said analog amplitude modulation signals.

16. The amplifier circuit of claim 13 further comprising an impedance adjusting element linked to said amplifiers.

17. The circuit of claim 13, wherein said class E amplifiers each include envelope adjustment circuitry to adjust the power level for each amplifier in said circuit.

18. The amplifier circuit of claim 13 wherein at least two of said amplifiers have different output power ratings.

19. The circuit of claim 13, wherein said converters are capable of processing at a high bit rate to output high-resolution analog signals corresponding to the signals received from the digital signal processor.

20. The circuit of claim 13, wherein said digital signal processor includes:

two amplitude-modulated outputs linked via separate digital to analog converters to each of two of said amplifiers; and

a quadrature modulating upconverter and a bandpass filter in series communication with each of said phase-modulated outputs of said digital signal processor.

21. The circuit of claim 13 further comprising means for modulating the input to at least one of said amplifiers.

22. The circuit of claim 13 further comprising:

a feedback loop for sensing VSWR reflection from an antenna in communication with one of said amplifiers, said feedback loop in communication with said digital signal processor;

wherein said digital signal processor adjusts said waveforms to correct for said VSWR reflection.

23. A method of providing high-efficiency and high peak-to-average signal amplification, said method comprising the steps of:

providing first and second digital amplitude waveforms from a digital signal processor;

providing a first digital phase waveform from said digital signal processor;

converting said first digital amplitude waveform into a first analog amplitude waveform, and said second digital amplitude waveform into a second analog amplitude waveform;

converting said first digital phase waveform into a first analog phase waveform;

generating a first output signal with a carder amplifier from said first analog amplitude waveform and said first analog phase waveform;

generating a second output signal with a peaking amplifier from said second analog amplitude waveform and said second analog phase waveform; and

combining said first and second output signals.

24. The method of claim 23 further comprising the steps of:

sensing VSWR reflection from an antenna in communication with one of said amplifiers; and

adjusting said digital amplitude and phase waveforms within said processor to correct for said VSWR reflection.