Low-power, low-noise dual gain amplifier topology and method

• US 6,396,347 B1
• Filed: 05/03/2001
• Issued: 05/28/2002
• Est. Priority Date: 05/03/2001
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lie, Donald Y., Larson, Lawrence E.
• Primary Examiner(s): Lee, Benny T.
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/848,855
• Time in Patent Office: 390 Days
• Field of Search: 330/133,134,285,311,300,51,129,295,84
• US Class Current: 330/285
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

In a low-heightened power, low-heightened noise dual gain amplifier, first and second, transistors have their emitter-collector circuits connected in series between the ground and a bus voltage. A radio frequency input terminal is coupled to the bases of both transistors. The first transistor is connected across the ground and an output terminal and operated in the common emitter mode. The first transistor operates as a high gain amplifier. A second transistor is connected across the output terminal and a bus voltage. First and second switching transistors switch first and second biasing sources to render first and second amplifier transistors conducted for operation in the high gain or low gain mode. Additionally, a third switching transistor is ac coupled across the input terminals of the first and second amplifier transistors. The third switching transistor is biased along with the first switching transistor for selectively coupling the RF input to the high gain or low gain amplifying transistor.

Claims

1. A low-power, low-noise, dual gain amplifier comprising:

first and second amplifier transistors each coupled for receiving a radio frequency input, said first amplifier transistor comprising a high gain amplifier and connected for operating in common emitter mode, and said second amplifier transistor comprising a low gain amplifier and connected for operating in the common collector mode, said first and second amplifier transistors being connected for alternate activation.

2. The amplifier according to claim 1 further comprising first and second bias sources connected to the bases of said first and second amplifier transistors respectively and first and second switching transistors coupled across said first and second bias sources and switch biasing means for biasing said first and second switching transistors to opposite conductivity states, whereby one of said first and second amplifier transistors is activated while the other is inactivated.

3. The amplifier according to claim 2 further comprising a third switching transistor ac coupled between inputs to said first and second amplifier transistors, said third switching transistor coupled to said switch biasing means to control its conductivity state.

4. The amplifier according to claim 3 in which said switch biasing means biases said second and third switching transistors to a one conductivity state and said first switching transistor to an opposite conductivity state and wherein the collector of said first amplifier transistor and the emitter of said second amplifier transistor are connected to an output terminal of said amplifier.

5. The amplifier according to claim 4 wherein said switching transistors comprise MOSFET transistors and said amplifier transistors comprise heterojunction bipolar transistors.

6. The amplifier according to claim 5 wherein said first and second amplifier transistors comprise N-P-N transistors.

7. A method of amplifying a radio frequency signal at a selected gain level comprising the steps of providing first and second amplifier transistors for coupling to the signal, said first and second amplifier transistors being connected in the common emitter and the common collector modes respectively, selectively alternately activating said first and second amplifier transistors and amplifying the signal at a high gain with said first amplifier transistor and multiplying said the signal at a low gain with said second amplifier transistor.

8. A method according to claim 7 wherein the step of alternately activating comprises switching bias currents connected to the bases of said first and second amplifier transistors.

9. A method according to claim 7 wherein the step of alternately activating further comprises opening or closing an ac path between the inputs of the first and second power transistors.

10. The method according to claim 7 wherein the step of providing said first and second amplifier transistors comprises providing first and second N-P-N transistors.