Embedded mechanism offering real-time self failure detection for an analog to digital converter
First Claim
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1. A method of testing an analog-to-digital converter (ADC) comprising:
- connecting an input signal having a predetermined voltage range to an input terminal of said ADC;
connecting, during a first sample period, a reference voltage to said input terminal, said reference voltage being outside of said voltage range;
disconnecting said reference voltage during a second sample period, said input signal remaining connected to said input terminal;
converting voltage on said input terminal to a digital value during a conversion period;
comparing said digital value to a predetermined set of digital values, said predetermined set corresponding to said voltage range; and
detecting a failure of said ADC if said digital value is outside said predetermined set.
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Abstract
This invention describes a real-time failure detection system for the inputs of an analog-to-digital converter. A novel mechanism is proposed that provides recognition of an ADC input pin failure through the digital result obtained. The device includes a specific hardware architecture which can be added to any ADC core. This is especially useful in safety applications (where FMEA is a main concern), as it greatly increases the reliability of the analog data measured.
48 Citations
28 Claims
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1. A method of testing an analog-to-digital converter (ADC) comprising:
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connecting an input signal having a predetermined voltage range to an input terminal of said ADC;
connecting, during a first sample period, a reference voltage to said input terminal, said reference voltage being outside of said voltage range;
disconnecting said reference voltage during a second sample period, said input signal remaining connected to said input terminal;
converting voltage on said input terminal to a digital value during a conversion period;
comparing said digital value to a predetermined set of digital values, said predetermined set corresponding to said voltage range; and
detecting a failure of said ADC if said digital value is outside said predetermined set. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of operating an analog-to-digital converter (ADC) to provide self failure detection comprising:
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generating a first sample period in which a sample and hold circuit in said ADC receives a signal applied to an Input terminal of said ADC;
applying, during said first sample period, an input signal to said input terminal, said input signal having a predetermined amplitude range;
applying, during said first sample period, a reference signal having an amplitude higher than or lower than said predetermined amplitude range, to said input terminal;
generating a second sample period in which said sample and hold circuit receives and holds a signal applied to said input terminal;
applying, during said second sample period, only said input signal to said input terminal, generating a conversion period during which a value held in said sample and hold circuit is converted into a digital value;
determining if said digital value corresponds to said amplitude of said reference signal or is shifted towards said amplitude of said reference signal; and
detecting a failure on determining said correspondence or shifting. - View Dependent Claims (8, 9, 10, 11, 12)
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13. An analog to digital converter (ADC) having self-test capabilities comprising:
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an input terminal for being coupled to an input signal having a predetermined amplitude range;
a sample and hold circuit coupled to said input terminal;
a converter coupled to said sample and hold circuit;
a control circuit coupled to said sample and hold circuit and to said converter for generating a control signal to provide first and second sample periods and a conversion period;
a switch coupled to said input terminal and responsive to said control signal for applying a reference signal to said input terminal during said first sample period and not during said second sample period, said reference signal being outside of said predetermined amplitude range; and
a comparator coupled to an output of said ADC for determining a failure if a digital value generated by said ADC which corresponds to said amplitude of said input signal is outside a range of values which correspond to said predetermined amplitude range. - View Dependent Claims (14, 15, 16, 17)
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18. A system for analog-to-digital conversion (ADC system) comprising:
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a self-test controller;
a real-time failure detection circuit controlled by said self-test controller for detecting failures in said ADC system, said failure detection circuit generating at least a first reference signal which is outside a range of values expected as an input signal;
an analog-to-digital converter (ADC) for sampling said input signal and converting said sample to a digital value;
wherein said failure detection circuit applies said reference signal and said input signal to said ADC during a first sample period and only said input signal during a second sample period, and compares a converted output against an expected output range whereby a failure of said ADC system is determined if said converted output is outside said expected output range. - View Dependent Claims (19, 20, 21, 22)
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23. An engine control system comprising:
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a sensor for sensing a state of operation of an engine and generating a monitor signal;
an analog-to-digital converter (ADC) for sampling said monitor signal and converting said sample to a digital value;
a self-test controller;
a real-time failure detection circuit controlled by said self-test controller for detecting failures in said system, said failure detection circuit generating at least a first reference signal which is outside a range of values expected of said monitor signal, wherein said failure detection circuit applies said reference signal and said input signal to said ADC during a first sample period and only said input signal during a second sample period, and compares a converted output against an expected output range whereby a failure of said system is determined if said converted output is outside said expected output range. - View Dependent Claims (24, 25, 26, 27, 28)
a memory for storing data;
input/output ports for gathering and transmitting data;
a memory unit for storing said digital value, and wherein said failure detection circuit comprises a control unit and status sequencer for analyzing said digital value and indicating failure of said analog-to-digital conversion.
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25. The system of claim 23 wherein said real-time failure detection unit includes a switch for applying a first reference signal having an amplitude below said predetermined amplitude range and a second reference signal which exceeds said predetermined amplitude range.
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26. The ADC of claim 23 wherein said first and second reference signals have amplitudes that are programmable.
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27. The ADC of claim 23 wherein said failure of said ADC is one of an open circuit on an input signal line, a short circuit to power supply voltage on said input signal line and a short circuit to ground on said input signal line.
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28. The ADC of claim 23 further comprising a selection circuit coupled to said input terminal for selecting as said input signal one of a plurality of input signals.
Specification