System and method for monitoring the operation of a power converter
First Claim
1. A circuit for monitoring the voltage spikes occurring in a power converter system containing a bus having a resistive parameter (R) and an inductive parameter (L) comprising:
- a first comparator circuit having first and second inputs;
a first reference level voltage source connected to the first input of the first comparator circuit for providing a first voltage level input signal;
a second comparator circuit having first and second inputs;
a second reference level voltage source connected to the second input of the second comparator circuit to provide a second voltage level input signal;
a dc voltage blocking circuit;
the second input of the first comparator circuit and the first input of the second comparator circuit being connected in common through the dc voltage blocking circuit to the bus of the power converter system and responsive to a voltage spike (Vspike) thereon;
wherein the first comparator circuit produces an output signal when a voltage spike on the bus exceeds the voltage level of the first voltage level input signal, and wherein the second comparator circuit produces an output signal when a voltage spike on the bus is lower than the voltage level of the second voltage level input signal.
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Abstract
A fault detection circuit and method for monitoring a power converter system to identify faults. The detection circuit includes two comparator circuits each having one input connected to the dc bus of the power converter system and responsive to the voltage spikes that occur as a result of faults. The other inputs of the comparator circuits are respectively connected to first and second sources of reference voltages having preset limits. The outputs of the two comparator circuits are combined on an output lead, and a fault signal will be produced on the output lead when the voltage spike on the dc bus exceeds the limits.
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Citations
8 Claims
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1. A circuit for monitoring the voltage spikes occurring in a power converter system containing a bus having a resistive parameter (R) and an inductive parameter (L) comprising:
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a first comparator circuit having first and second inputs;
a first reference level voltage source connected to the first input of the first comparator circuit for providing a first voltage level input signal;
a second comparator circuit having first and second inputs;
a second reference level voltage source connected to the second input of the second comparator circuit to provide a second voltage level input signal;
a dc voltage blocking circuit;
the second input of the first comparator circuit and the first input of the second comparator circuit being connected in common through the dc voltage blocking circuit to the bus of the power converter system and responsive to a voltage spike (Vspike) thereon;
wherein the first comparator circuit produces an output signal when a voltage spike on the bus exceeds the voltage level of the first voltage level input signal, and wherein the second comparator circuit produces an output signal when a voltage spike on the bus is lower than the voltage level of the second voltage level input signal. - View Dependent Claims (2, 3, 4)
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5. A method for monitoring the voltage spikes (Vspike) occurring in a power converter system containing a bus having a resistive parameter (R) and an inductive parameter (L) comprising the steps of:
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A. providing a first reference level voltage signal;
B. providing a second reference level voltage signal;
C. blocking the dc components of the bus voltage and providing the remaining voltage to a sensing resistor (Rsense ) in the bus of the power converter system;
D. comparing the voltage across the sensing resistor (Rsense) with the first reference level signal to provide a first comparison signal when the voltage across the sensing resistor is greater than the first reference level signal; and
E. comparing the voltage across the sensing resistor (Rsense) with the second reference level signal to provide a second comparison signal when the voltage across the sensing resistor is lower than the second reference signal. - View Dependent Claims (6, 7, 8)
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Specification