Memory system having flexible bus structure and method
First Claim
1. A memory device comprising:
- a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, with the system bus interface including a bi-directional data bus interface to be coupled to the data bus and a tag bus interface to be coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, with said memory operation manager being configured to carry out memory read operations on the array in response to receipt of a memory read command set which includes at least one command and to carry out memory program operations on the array in response to receipt of a memory program command set which includes at least one command and a bus direction controller configured to cause the data bus interface to be set to a direction for transfer of data read from the memory array during the memory read operations and to cause the data bus interface to be set to a direction for transfer of data to the memory device for programming into the array during the memory program operations.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.
16 Citations
33 Claims
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1. A memory device comprising:
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a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, with the system bus interface including a bi-directional data bus interface to be coupled to the data bus and a tag bus interface to be coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, with said memory operation manager being configured to carry out memory read operations on the array in response to receipt of a memory read command set which includes at least one command and to carry out memory program operations on the array in response to receipt of a memory program command set which includes at least one command and a bus direction controller configured to cause the data bus interface to be set to a direction for transfer of data read from the memory array during the memory read operations and to cause the data bus interface to be set to a direction for transfer of data to the memory device for programming into the array during the memory program operations. - View Dependent Claims (2, 3, 4)
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5. A memory device, comprising:
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a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface; and
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations. - View Dependent Claims (6, 7, 8, 9)
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10. A memory device, comprising:
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a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface, the memory operation manager including a control register that stores control data for the memory operations;
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations; and
wherein memory operation command set includes a read control register command and the bus direction controller sets the data transfer direction to out of the data bus interface to the system data bus. - View Dependent Claims (11, 12, 13)
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14. A memory device, comprising:
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a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface; and
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations, wherein the bus direction controller includes a command decoder adapted to produce an input enable signal based on the memory command set received by the memory operation manager. - View Dependent Claims (15, 16, 17, 18)
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19. A memory device, comprising:
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a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface; and
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations, wherein the bus direction controller includes a command decoder adapted to produce an Out/In signal based on the memory command set received by the memory operation manager. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A memory system including a plurality of memory devices and a system bus, the system bus including a tag bus and a data bus, each memory device comprising:
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a system bus interface to be coupled to the system bus, the system bus interface including a bi-directional data bus interface connected to the data bus and a tag bus interface connected to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory read operations on the array in response to receipt of a memory read command set which includes at least one command and to carry out memory program operations on the array in response to receipt of a memory program command set which includes at least one command; and
a bus direction controller configured to cause the data bus interface to be set to a direction for transfer of data read from the memory array during the memory read operations and to cause the data bus interface to be set to a direction for transfer of data to the memory device for programming into the array during the memory program operations. - View Dependent Claims (26)
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27. A memory system including a plurality of memory devices and a system bus, the system bus including a data bus and a tag bus, each memory device comprising:
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a system bus interface to be coupled to the system bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface; and
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations. - View Dependent Claims (28, 29, 30)
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31. A memory system including a plurality of memory devices and a system bus, the system bus including a data bus and a tag bus, each memory device comprising:
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a system bus interface to be coupled to the system bus, the system bus interface including a bi-directional data bus interface coupled to the data bus and a tag bus interface coupled to the tag bus;
an array of memory cells;
a memory operation manager operably coupled to the system bus interface and to the array of memory cells, the memory operation manager being configured to carry out memory operations on the array in response to receipt of a memory operation command set on the tag bus interface, the memory operation manager including a control register that stores control data for the memory operations;
a bus direction controller configured to set a data transfer direction of the data bus interface during the memory operations; and
wherein memory operation command set includes a read control register command and the bus direction controller sets the data transfer direction to out of the data bus interface to the system data bus. - View Dependent Claims (32, 33)
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Specification