Magneto-resistive memory having sense amplifier with offset control

• US 6,396,733 B1
• Filed: 07/17/2000
• Issued: 05/28/2002
• Est. Priority Date: 07/17/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lu, Yong, Dries, Michael F.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/618,256
• Time in Patent Office: 680 Days
• Field of Search: 365/158,207,206,205
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence

Abstract

A magneto-resistive memory is disclosed that includes a high-speed sense amplifier that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

Claims

1. A magneto-resistive memory, comprising:

magneto-resistive memory means having a first magneto-resistive bit with a first end and a second end and a second magneto-resistive bit with a first end and a second end, the first end of the first magneto-resistive bit is coupled to a first bit line and the first end of the second magneto-resistive bit is coupled to a second bit line, the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit are selectively coupled to a predetermined reference voltage via a switching means;

current providing means for providing current to the first and second bit lines;

sensing means for sensing a differential voltage signal between the first and second bit lines;

amplifier means having an input, an output and offset cancellation, the offset cancellation of the amplifier means is controlled at least in part by one or more switches, the amplifier means providing an output signal;

providing means for providing the voltage signal of the sensing means to the input of the amplifier means;

control means for enabling the one or more switches of the amplifier means to enable the offset cancellation, and for subsequently disabling the one or more switches for disabling the offset cancellation, the control means also enabling the switching means of the magneto-resistive memory means; and

storing means for storing the output signal of the amplifier means after the one or more switches of the amplifier means are disabled.

2. A magneto-resistive memory according to claim 1, wherein the providing means provides the voltage signal to the amplifier means before the one or more switches of the amplifier means are disabled by the control means.

3. A magneto-resistive memory according to claim 1, wherein the providing means provides the voltage signal to the amplifier means after the one or more switches of the amplifier means are disabled by the control means.

4. A magneto-resistive memory according to claim 1, wherein the one or more switches of the amplifier means selectively connect the input of the amplifier means to a predetermined voltage.

5. A magneto-resistive memory according to claim 1, wherein the one or more switches of the amplifier means selectively connect the output of the amplifier means to a predetermined voltage.

6. A magneto-resistive memory according to claim 1, wherein the one or more switches of the amplifier means selectively connect the input of the amplifier means to the output of the amplifier means.

7. A magneto-resistive memory according to claim 1, wherein the providing means provides the voltage signal to the input of the amplifier means through one or more coupling capacitors.

8. A magneto-resistive memory according to claim 1 wherein the amplifier means includes one or more coupling capacitors in series with the output of the amplifier means.

9. A magneto-resistive memory, comprising:

magneto-resistive memory means having a first magneto-resistive bit with a first end and a second end and a second magneto-resistive bit with a first end and a second end, the first end of the first magneto-resistive bit is coupled to a first bit line and the first end of the second magneto-resistive bit is coupled to a second bit line, the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit are selectively coupled to a predetermined reference voltage via a switching means;

current providing means for providing current to the first and second bit lines;

sensing means for sensing a differential voltage signal between the first and second bit lines;

amplifier means having an input and an output, the amplifier means having an auto-zero means for selectively connecting the input of the amplifier means to the output of the amplifier means, the amplifier means providing an output signal;

providing means for providing the voltage signal of the sensing means to the input of the amplifier means through one or more coupling capacitors;

control means coupled to the amplifier means for enabling the auto-zero means of the amplifier means, and for subsequently disabling the auto-zero means of the amplifier means, the control means also enabling the switching means of the magneto-resistive memory means; and

storing means for storing the output signal of the amplifier after the auto-zero means of the amplifier means is disabled.

10. A magneto-resistive memory according to claim 9, wherein the providing means provides the voltage signal to the input of the amplifier means before the control means disables the auto-zero means.

11. A magneto-resistive memory according to claim 9, wherein the providing means provides the voltage signal to the input of the amplifier means after the control means disables the auto-zero means.

12. A magneto-resistive memory according to claim 9, wherein the auto-zero means of the amplifier selectively connects the input of the amplifier means to a predetermined voltage.

13. A magneto-resistive memory according to claim 9, wherein the voltage signal is a differential voltage signal defined by the difference between a first voltage signal and a second voltage signal.

14. A magneto-resistive memory according to claim 13, wherein the input of the amplifier means is a differential input having a first input terminal and a second input terminal.

15. A magneto-resistive memory according to claim 14, wherein the providing means provides the first voltage signal to the first input terminal of the amplifier means through a first coupling capacitor, and provides the second voltage signal to the second input terminal of the amplifier means through a second coupling capacitor while the auto-zero means of the amplifier is enabled.

16. A magneto-resistive memory according to claim 15, wherein the providing means provides the first voltage signal to the second input terminal of the amplifier means via the first coupling capacitor, and provides the second voltage signal to the first input terminal of the amplifier means via the second coupling capacitor when the auto-zero means of the amplifier is disabled.

17. A magneto-resistive memory according to claim 9, wherein the providing means includes a preamplifier for amplifying the voltage signal before the voltage signal is provided to the input of the amplifier means through the one or more coupling capacitors.

18. A magneto-resistive memory according to claim 9, wherein said storing means includes a latching element, wherein the latching element includes a pair of cross-coupled inverters, each of the cross-coupled inverters having an output terminal and a power supply terminal that can be selectively disconnected, the latching element further having at least two switching means for selectively connecting the output signal of the amplifier to at least one of the output terminals of the cross-coupled inverters, and a reset switch for selectively connecting together the output terminals of the cross-coupled inverters.

19. A magneto-resistive memory according to claim 18, wherein the control means selectively disconnects the power supply terminals of each of the cross-coupled inverters of the latching element;

enables the at least two switching means of the latching element to allow the output signal of the amplifier to set the voltage levels of at least one of the output terminals of the cross-coupled inverters;

disables the at least two switching means of the latching element to prevent the output signal of the amplifier from setting the voltage levels of the output terminals of the cross-coupled inverters;

selectively connects the power supply terminals of each of the cross-coupled inverters of the latching element, thereby setting the state of the latching element to a desired state;

reads the state of the latching element;

selectively disconnects the power supply terminals of each of the cross-coupled inverters of the latching element; and

resets the state of the latching element by selectively connecting the output terminals of the cross-coupled inverters via the reset switch.

20. A method for sensing the state of one or more magneto-resistive elements, the method comprising the steps of:

providing current through the one or more magneto-resistive elements;

sensing a voltage signal across the one or more magneto-resistive elements;

providing an amplifier with offset cancellation, wherein the offset cancellation is controlled at least in part by one or more switches, the amplifier providing an output signal;

enabling the one or more switches to enable the offset cancellation of the amplifier;

disabling the one or more switches;

providing the voltage signal to the amplifier; and

storing the output signal of the amplifier.

21. A method according to claim 20, wherein the voltage signal is provided to the amplifier before the one or more switches are disabled.

22. A method according to claim 20, wherein the voltage signal is provided to the amplifier after the one or more switches are disabled.

23. A method according to claim 20, wherein the one or more switches selectively connect an input of the amplifier to a predetermined voltage.

24. A method according to claim 20, wherein the one or more switches selectively connect an output of the amplifier to a predetermined voltage.

25. A method according to claim 20, wherein the one or more switches selectively connect an input of the amplifier to an output of the amplifier.

26. A method according to claim 20, wherein the voltage signal is provided to the amplifier through one or more coupling capacitors.

27. A method according to claim 20, wherein the amplifier includes one or more coupling capacitors in series with an output of the amplifier.

28. A method for sensing the state of one or more magneto-resistive elements, the method comprising the steps of:

providing a current through the one or more magneto-resistive elements;

sensing a voltage signal across the one or more magneto-resistive elements;

providing an amplifier having an input and an output, the amplifier having an auto-zero capability for selectively connecting the input to the output, the amplifier providing an output signal;

enabling the auto-zero capability of the amplifier;

providing the voltage signal to the input of the amplifier through one or more coupling capacitors;

disabling the auto-zero capability of the amplifier; and

storing the output signal of the amplifier after the auto-zero capability is disabled.

29. A method according to claim 28, wherein the voltage signal is provided to the input of the amplifier before the auto-zero capability of the amplifier is disabled.

30. A method according to claim 28, wherein the voltage signal is provided to the input of the amplifier after the auto-zero capability of the amplifier is disabled.

31. A method according to claim 28, wherein the auto-zero capability of the amplifier further selectively connects the input of the amplifier to a predetermined voltage.

32. A method according to claim 28, wherein the voltage signal is a differential voltage signal defined by the difference between a first voltage signal and a second voltage signal.

33. A method according to claim 32, wherein the input of the amplifier is a differential input having a first input terminal and a second input terminal.

34. A method according to claim 33, wherein the first voltage signal is provided to the first input terminal of the amplifier via a first coupling capacitor, and the second voltage signal is provided to the second input terminal of the amplifier via a second coupling capacitor when the auto-zero capability of the amplifier is enabled.

35. A method according to claim 34, further comprising the step of providing the first voltage signal to the second input terminal of the amplifier via the first coupling capacitor, and the second voltage signal is provided to the first input terminal of the amplifier via the second coupling capacitor when the auto-zero capability of the amplifier is disabled.

36. A method according to claim 28, further comprising the step of amplifying the voltage signal before the voltage signal is provided to the input of the amplifier through the one or more coupling capacitors.

37. A method according to claim 28, further wherein said storing step includes the step of latching the output signal of the amplifier into a latching element, wherein the latching element includes a pair of cross-coupled inverters, each of the cross-coupled inverters having an output terminal and a power supply terminal that can be selectively disconnected.

38. A method according to claim 37, wherein the latching step includes the steps of:

selectively disconnecting the power supply terminal of each of the cross-coupled inverters of the latching element;

allowing the output signal of the amplifier to set the voltage levels of the output terminals of the cross-coupled inverters;

preventing the output signal of the amplifier from setting the voltage levels of the output terminals of the cross-coupled inverters;

selectively connecting the power supply terminals of each of the cross-coupled inverters of the latching element, thereby setting the state of the latching element to a desired state;

reading the state of the latching element;

selectively disconnecting the power supply terminals of each of the cross-coupled inverters of the latching element; and

selectively connecting the output terminals of the cross-coupled inverters.

39. A method according to claim 38, wherein the output signal of the amplifier is prevented from setting the state of the latching element before the auto-zero capability of the amplifier is again enabled.