Testing of multilevel semiconductor memory

• US 6,396,742 B1
• Filed: 07/28/2000
• Issued: 05/28/2002
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, Korsh, George J., Khan, Sakhawat M.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/627,917
• Time in Patent Office: 669 Days
• Field of Search: 365/185.03,201,185.29,185.22,185.18
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.

Claims

1. A method for testing a multilevel memory, the method comprising:

performing an erase operation to place a plurality of memory cells in an erased state;

programming a state of each cell in a group of the plurality of cells to within a first range of voltages;

if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing;

if a state of each cell in the group of cells verifies to within the first range of voltages;

applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and

verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.

2. The method of claim 1 further comprising:

if a state of each of one or more cells in the group of cells is programmed beyond the second range of voltages, identifying at least the one or more cells as failing.

3. The method of claim 1 wherein the verifying step comprises:

comparing a sensing voltage generated by each of the further programmed cells to a preselected one of a plurality of reference voltages, the preselected reference voltage corresponding to the second range of voltages.

4. The method of claim 1 wherein the step of programming to within a first range of voltages is performed in accordance with an iterative verify-program routine.

5. The method of claim 1 wherein if a state of each cell in the group of cells verifies to within the first range of voltages, no verify operation is performed before or during the applying step.

6. The method of claim 1 further comprising:

if a state of each cell in the group of cells verifies to within the first range of voltages;

prior to the applying step, overriding a verify operation in an iterative verify-program routine; and

after the applying step, enabling the verify operation.

7. The method of claim 1 wherein the verifying step comprises:

identifying cells whose state fall short of the second range due to slow programming as passing.

8. The method of claim 1 wherein each of the predetermined number of programming pulses causes a sensing voltage generated by each cell in the group of memory cells to shift by a predetermined amount.

9. The method of claim 1 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

10. The method of claim 1 wherein the cells in the group of cells are tested simultaneously to identify the cells which exhibit overshoot or aliasing.

11. The method of claim 1 wherein the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the identifying step comprising:

reconfiguring the plurality of sequentially defined voltage ranges such that the first range in not used in all subsequent operations for at least the one or more cells.

12. The method of claim 2 wherein the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the identifying step after the applying step comprises:

reconfiguring the plurality of sequentially defined voltage ranges such that the second range is not used in all subsequent memory operations for at least the one or more cells.

13. The method of claim 2 wherein each of the identifying steps comprises:

storing an address of each of the one or more cells; and

avoiding the address of the one or more cells in accessing the multilevel memory.

14. The method of claim 2 wherein each of the identifying steps comprises:

identifying as defective one or more pre-defined sectors of cells which include the one or more cells.

15. The method of claim 2 wherein each of the identifying steps comprises:

storing an address of each of one or more predefined sectors of cells which include the one or more cells; and

avoiding the address of the one or more sectors of cells in accessing the multilevel memory.

16. The method of claim 15 wherein the avoiding step comprises:

mapping out the address of the one or more sectors of cells from a system'"'"'s memory space.

17. The method of claim 2 wherein each of the identifying steps comprises:

invoking redundancy to replace at least the one or more cells in the group of cells with redundant cells.

18. The method of claim 1 wherein the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the first range being the next range from the initial range.

19. The method of claim 1 wherein the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the first range being one of a first group of the plurality of sequentially defined voltage ranges substantially close to the initial range.

20. The method of claim 19 wherein the second range is one of a second group of the plurality of sequentially defined voltage ranges substantially close to the first range.

21. The method of claim 19 wherein the second range is the next range from the first range.

22. The method of claim 19 wherein a distribution of sensing voltages corresponding to the first range is narrower than a distribution of sensing voltages corresponding to the second range, the sensing voltages being generated by the group of cells.

23. The method of claim 19 wherein each of the plurality of sequentially defined voltage ranges corresponds to one of a plurality of distributions of sensing voltages generated by the memory cells.

24. The method of claim 23 wherein each sensing voltage is generated by a selected memory cell on a column line to which the selected cell is coupled.

25. The method of claim 23 wherein each of the plurality of sequentially defined voltage ranges is within a corresponding larger range of voltages, each larger range corresponding to one of 2^N binary combinations of N bits of data capable of being stored in each cell, wherein N is a positive integer.

26. The method of claim 25 wherein each of the larger voltage ranges has a magnitude less than 150 mV.

27. The method of claim 25 wherein N is greater than 2.

28. The method of claim 25 wherein the larger ranges are non-overlapping.

29. The method of claim 25 wherein each of the predetermined number of programming pulses causes a sensing voltage generated by each cell in the group of memory cells to shift by a predetermined amount.

30. The method of claim 29 wherein the first voltage range, the second voltage range, and the voltage ranges between the first and second voltage ranges have substantially equal magnitudes M1.

31. The method of claim 30 wherein the predetermined amount of sensing voltage shift is less than M1.

32. The method of claim 31 wherein the larger range corresponding to the first voltage range, and the larger range corresponding to the second voltage range, and the larger ranges corresponding to the voltage ranges between the first and second voltage ranges have substantially equal magnitudes M2.

33. The method of claim 32 wherein the predetermined number of programming pulses substantially equals M2 divided by the predetermined amount of sensing voltage shift if the second range is the next range from the first range.

34. The method of claim 32 wherein the second range is at least two ranges away from the first range.

35. The method of claim 34 wherein the predetermined number of programming pulses substantially equals the number of ranges the second range is away from the first range multiplied by M2 divided by the predetermined amount of sensing voltage shift.

36. The method of claim 32 wherein if the second range is the next range from the first range and the first range has a smaller magnitude than the second range then the predetermined number of programming pulses is substantially equal to M2 plus the difference between the magnitude of the second range and the magnitude of the first range, all divided by the predetermined amount of sensing voltage shift.

37. A method of testing a multilevel memory, the method comprising:

performing an erase operation to place a plurality of memory cells in an erased state;

programming a state of each cell in a group of the plurality of cells to within a first range of voltages;

if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing;

if a state of each cell in the group of cells verifies to within the first range of voltages;

overriding a verify operation in an iterative verify-program routine;

applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and

enabling the verify operation in the iterative verify-program routine;

verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages; and

if a state of each of one or more cells in the group of cells is programmed beyond the second range of voltages, identifying at least the one or more cells as failing.

38. The method of claim 37 wherein the verifying step comprises:

comparing a sensing voltage generated by each of the further programmed cells to a preselected one of a plurality of reference voltages, the preselected reference voltage corresponding to the second range.

39. The method of claim 37 wherein the programming step is performed in accordance with the iterative verify-program routine.

40. The method of claim 37 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

41. The method of claim 37 wherein the programming step further comprises:

comparing a sensing voltage generated by each of the programmed cells to a preselected pair of a plurality of reference voltages, the preselected pair of reference voltages corresponding to the first range.

42. The method of claim 37 wherein the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the first range being the next range from the initial range.

43. The method of claim 42 wherein each of the plurality of sequentially defined voltage ranges corresponds to one of a plurality of distributions of sensing voltages generated by the memory cells, each of the plurality of sequentially defined voltage ranges being within a corresponding larger range of voltages, each larger range corresponding to one of 2^N binary combinations of N bits of data capable of being stored in each cell, N being a positive integer, and the larger ranges being non-overlapping.

44. The method of claim 43 wherein each of the predetermined number of programming pulses causes a sensing voltage generated by each cell in the group of memory cells to shift by a predetermined amount, the sequentially defined voltage ranges having substantially equal magnitudes M1, the predetermined amount of sensing voltage shift being less than M1, a predetermined number of the larger ranges having substantially equal magnitudes M2.

45. The method of claim 43 wherein each of the larger voltage ranges has a magnitude less than 150 mV.

46. The method of claim 43 wherein N is greater than 2.

47. A method for detecting aliasing and overshoot in programming multilevel memory cells, the method comprising:

providing a plurality of sequentially defined voltage ranges which start with an initial range corresponding to an erased state, and a last range corresponding to a highest programmed state; and

applying a predetermined number of programming pulses to a plurality of cells to change a state of the cells from a first range of the sequentially defined voltage ranges other than the initial range to a second range of the sequentially defined voltage ranges.

48. The method of claim 47 wherein no verify operation is performed immediately before or during the applying step.

49. The method of claim 47 wherein each of the plurality of sequentially defined voltage ranges has a magnitude less than 150 mV.

50. The method of claim 47 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

51. A method for testing multilevel memory, the method comprising:

defining a plurality of sequentially defined voltage ranges which start with an initial range corresponding to an erased state and a last range corresponding to a highest programmed state;

identifying one or more memory cells failing to properly function in a target voltage range; and

reconfiguring the plurality of sequentially defined voltage ranges such that the target voltage range is not used in any subsequent memory operations for at least the one or more cells.

52. The method of claim 51 wherein the identifying step comprises:

identifying one or more memory cells which;

(a) fail to maintain stored charge in accordance with predefined criteria, or (b) upon applying a predetermined set of programming parameters program to a state corresponding to a voltage range beyond a target voltage range, or (c) upon applying a predetermined set of programming parameters fail to reach a state corresponding to a target voltage range, or (d) fail to properly erase from a target voltage range.

53. The method of claim 51 wherein each of the plurality of voltage ranges corresponds to one of 2^N binary combinations of N bits of data capable of being stored in memory cells, wherein N is a positive integer.

54. The method of claim 53 wherein the reconfiguring step comprises:

reducing the number of data bits capable of being stored in at least the one or more cells to an integer less than N.

55. The method of claim 53 wherein N is greater than 2.

56. The method of claim 51 wherein each of the plurality of sequentially defined voltage ranges has a magnitude less than 150 mV.

57. The method of claim 51 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

58. A method for testing a multilevel memory, the memory having an array of erased memory cells arranged along rows and columns, each cell being capable of storing N bits of data by setting a state of each cell to within one of 2^N voltage ranges, the cells along each row being divided into M groups, each of the M groups having a plurality of adjacent memory cells, N and M being integers greater than 1, wherein in a memory access one of a plurality of pages of memory cells in a row is selected, each page having M memory cells, one cell from each of the M groups of cells, a subset of each page of M memory cells comprising 2^N cells, the method comprising:

(a) programming a state of each cell in a first group of 2^N cells located along each column to a respective one of the 2^N voltage ranges; and

(b) programming a state of each cell in a second group of cells comprising the 2^N cells in the subset of a selected page along each row, each of the 2^N cells in the subset of the selected page along each row being programmed to a respective one of the 2^N voltage ranges.

59. The method of claim 58 further comprising:

programming a state of each of 2^N reference cells along each row to a respective one of the 2^N voltage ranges; and

comparing a state of each of the 2^N cells in the subset of the selected page along each row to a state of a corresponding one of the 2^N reference cells along the same row.

60. The method of claim 58 wherein each of the M groups of cells comprises K adjacent memory cells, there being K pages of memory cells along each row, the method further comprising:

programming a state of each of the 2^N cells in the subset of each of the K pages along each row to a respective one of the 2^N voltage ranges.

61. The method of claim 60 wherein the multilevel memory further comprises K groups of reference cells along each row, each of the K groups of reference cells comprising 2^N reference cells, the method further comprising:

programming a state of each of the 2^N reference cells in each of the K groups of reference cells along each row to a respective one of the 2^N voltage ranges; and

comparing a state of each of the 2^N cells in each of the K subsets along each row to a state of a corresponding one of the 2^N reference cells in each of the K groups of reference cells along the same row.

62. The method of claim 58 wherein the first group of cells are located substantially along a first side of the array furthest from a column select circuit coupled to the columns, and the second group of cells are located substantially along a second side of the array furthest from a row select circuit coupled to the rows.

63. The method of claim 58 wherein the cells in the first group of 2^N cells located along each column are adjacent one another.

64. The method of claim 58 wherein in steps (a) and (b) no two adjacent cells along each row are programmed to a same voltage range.

65. The method of claim 58 wherein in steps (a) and (b) no two adjacent cells along each column are programmed to a same voltage range.

66. The method of claim 58 further comprising:

(c) programming a state of each cell in a third group of 2^N cells located along each column to a respective one of the 2^N voltage ranges, the third group of cells being located along a third side of the array substantially close to a column select circuit coupled to the columns; and

(d) programming a state of each cell in a fourth group of cells comprising 2^N cells in a subset of a selected page along each row, each of the 2^N cells in a subset of a selected page along each row in the fourth group being programmed to a respective one of the 2^N voltage ranges, the fourth group of cells being located along a fourth side of the array substantially close to a row select circuit coupled to the rows.

67. The method of claim 66 further comprising:

programming a state of each of the 2^N cells in the subset of each of the plurality of pages along each row in each of the second and fourth groups of cells to a respective one of the 2^N voltage ranges.

68. The method of claim 66 further comprising:

partially programming the remaining erased cells in the array of cells in accordance with a programming pattern as defined by steps (a), (b), (c), and (d).

69. The method of claim 58 wherein the 2^N voltage ranges are sequentially defined between a first voltage range corresponding to an erased state and a 2^N voltage range corresponding to a highest programmed state.

70. The method of claim 58 wherein each of the 2^N voltage ranges corresponds to one of 2^N binary combinations of the N bits of data.

71. The method of claim 58 further comprising:

partially programming the remaining erased cells in the array of cells in accordance with a programming pattern as defined by steps (a) and (b).

72. The method of claim 58 further comprising:

programming at least a portion of the remaining erased cells in the array of cells using a reduced value of N.

73. The method of claim 58 further comprising:

identifying cells failing to program in accordance with steps (a) and (b); and

programming a section or all of the remaining erased cells in the array of cells based on a number of failing cells identified in the identifying step.

74. The method of claim 58 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

75. The method of claim 58 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

76. The method of claim 58 wherein N is greater than 2.

77. A method for testing a multilevel memory having an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2^N voltage ranges, each of the 2^N voltage ranges comprising a distribution voltage range and at least one margin voltage range, N being an integer greater than 1, the method comprising:

programming a state of each of a plurality of the memory cells to within the distribution voltage range of at least one of the 2^N voltage ranges;

sensing the state of each of the plurality of programmed memory cells; and

identifying any of the programmed memory cells whose state resides within the at least one margin voltage range,

wherein a magnitude of the at least one margin voltage range is adjustable.

78. The method of claim 77 wherein the memory is an integrated circuit, the method further comprising:

internally generating a plurality of predefined margin voltage values used to define a magnitude of the at least one margin voltage range of each of the 2^N voltage ranges; and

externally selecting at least one of the plurality of predefined margin voltage values for defining a magnitude of at least one margin voltage range of at least one of the 2^N voltage ranges.

79. The method of claim 78 wherein the internally generated plurality of predefined margin voltage values are adjustable.

80. The method of claim 78 further comprising:

storing the externally selected one of the plurality of predefined margin voltage values in a storage element.

81. The method of claim 80 wherein the externally selected one of the plurality of predefined margin voltage values is stored as binary data.

82. The method of claim 77 further comprising:

replacing any cell identified in the identifying step with redundant memory cells.

83. The method of claim 77 further comprising:

reducing the number of data items N stored in any cells identified in the identifying step.

84. The method of claim 77 further comprising:

reconfiguring the 2^N voltage ranges such that one or more of the voltage ranges to which any cells identified in the identifying step were programmed are not used in all subsequent memory operations.

85. The method of claim 77 further comprising:

storing status information indicating whether any cells were identified in the identifying step.

86. The method of claim 85 wherein the sensing step corresponds to a normal memory read operation, the method further comprising:

interrogating the status information; and

executing a restore operation to restore the state of any cells identified in the identifying step to its original distribution range if the status information indicates that one or more cells were identified in the identifying step.

87. The method of claim 77 wherein the memory is an integrated circuit, the method further comprising:

storing address information of any cells identified in the identifying step in an internal storage element.

88. The method of claim 77 wherein the memory is an integrated circuit, the method further comprising:

storing address information of any cells identified in the identifying step in an external storage element.

89. The method of claim 77 wherein each of the 2^N voltage ranges comprises an upper-margin voltage range and a lower-margin voltage range, the method comprising:

identifying any of the programmed memory cells whose state resides within either the upper-margin voltage range or the lower-margin voltage range, wherein the upper-margin voltage range and the lower-margin voltage range of each of the 2^N voltage ranges are adjustable.

90. The method of claim 89 wherein the upper-margin voltage range, the distribution voltage range, and the lower-margin voltage range are non-overlapping voltage ranges.

91. The method of claim 77 wherein the 2^N voltage ranges are sequentially defined between a first voltage range corresponding to an erased state and a 2^N voltage range corresponding to a highest programmed state.

92. The method of claim 77 wherein each distribution voltage range is defined by a distribution of sensing voltages corresponding to one binary combination of the N bits of data.

93. The method of claim 77 wherein each of the 2^N voltage ranges corresponds to one of 2^N binary combinations of the N bits of data.

94. The method of claim 77 wherein the 2^N voltage ranges are non-overlapping voltage ranges.

95. The method of claim 77 wherein the sensing step comprises:

comparing a sensing voltage generated by each of the plurality of programmed memory cells on a corresponding column to which each cell is coupled to a preselected one of a plurality of reference voltages, the preselected reference voltage corresponding to the at least one margin voltage range, to indicate a state of the measured cell.

96. The method of claim 77 wherein the sensing step corresponds to a normal memory read operation, the method further comprising:

restoring the state of any cells identified in the identifying step to its original distribution range.

97. The method of claim 77 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

98. The method of claim 77 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

99. The method of claim 77 wherein N is greater than 2.

100. A method for testing a multilevel memory having an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2^N voltage ranges, each of the 2^N voltage ranges comprising a distribution voltage range and at least one margin voltage range, N being an integer greater than 1, the method comprising:

setting the distribution voltage range of at least one of the 2^N voltage ranges to a smaller range than a corresponding distribution voltage range used during normal memory programming mode;

programming a state of each of a plurality of the memory cells to within the distribution voltage range of the at least one of the 2^N voltage ranges;

subjecting the plurality of programmed cells to stress conditions; and

if a state of one or more of the programmed cells drifts a predetermined amount out of the smaller distribution voltage range, identifying the one or more of the programmed cells.

101. The method of claim 100 wherein the smaller distribution range is obtained by setting a magnitude of the at least one margin voltage range to be greater than a magnitude of the corresponding margin voltage range used during normal memory programming mode.

102. The method of claim 100 further comprising:

replacing any cell identified in the identifying step with redundant memory cells.

103. The method of claim 100 further comprising:

reducing the number of data items N stored in at least any cells identified in the identifying step.

104. The method of claim 100 further comprising:

reconfiguring the 2^N voltage ranges such that one or more of the voltage ranges to which any cells identified in the identifying step were programmed are not used in all subsequent memory operations.

105. The method of claim 100 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

106. The method of claim 100 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

107. The method of claim 100 wherein N is greater than 2.

108. The method of claim 100 wherein the memory is an integrated circuit, the predetermined amount corresponding to a tolerated-drift voltage range, the method further comprising:

internally generating a plurality of predefined tolerated-drift voltage values used to define a magnitude of the tolerated-drift voltage range of the at least one of the 2^N voltage ranges; and

externally selecting at least one of the plurality of predefined tolerated-drift voltage values for defining a magnitude of the tolerated-drift voltage range of at least one of the 2^N voltage ranges.

109. The method of claim 100 further comprising:

storing the externally selected at least one of the plurality of predefined tolerated-drift voltage values in a storage element.

110. The method of claim 109 wherein the externally selected one of the plurality of predefined margin voltage values is stored as binary data.

111. The method of claim 108 wherein the internally generated plurality of predefined tolerated-drift voltage values are adjustable.

112. The method of claim 108 wherein the smaller distribution voltage range, the at least one tolerated-drift voltage range, the at least one margin voltage range in the at least one of the 2^N voltage ranges are non-overlapping voltage ranges.

113. A method for testing a multilevel memory having an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2^N voltage ranges, N being an integer greater than 1, the method comprising:

dividing the 2^N voltage ranges into at least a first group of one or more voltage ranges and a second group of one or more voltage ranges;

programming a state of each of a plurality of the memory cells to within the second group of one or more voltage ranges;

sensing the state of each of the plurality of programmed memory cells; and

identifying any of the programmed memory cells whose state resides within the first group of one or more voltage ranges as failing.

114. The method of claim 113 wherein the 2^N voltage ranges are sequentially defined between a first voltage range corresponding to an erased state and a 2^N voltage range corresponding to a highest programmed state.

115. The method of claim 114 further comprising:

generating a plurality of reference voltages for uniquely identifying each of the 2^N voltage ranges; and

forcing all the plurality of reference voltages to be equal to a mid-reference voltage between the first voltage range and the 2^N voltage range.

116. The method of claim 114 wherein the dividing step comprises:

generating a mid-reference voltage, the mid-reference voltage being substantially near a center of the sequentially defined 2^N voltage ranges, voltage ranges above the mid-reference voltage corresponding to the first group of one or more voltage ranges, and voltage ranges below the mid-reference voltage corresponding to the second group of one or more voltage ranges.

117. The method of claim 116 further comprising:

generating a plurality of reference voltages for uniquely identifying each of the 2^N voltage ranges; and

forcing all the plurality of reference voltages to be equal to the mid-reference voltage.

118. The method of claim 114 wherein the dividing step comprises:

generating a mid-reference voltage, the mid-reference voltage being substantially near the 2^N voltage range, voltage ranges above the mid-reference voltage corresponding to the first group of one or more voltage ranges, and voltage ranges below the mid-reference voltage corresponding to the second group of one or more voltage ranges.

119. The method of claim 118 further comprising:

generating a plurality of reference voltages for uniquely identifying each of the 2^N voltage ranges; and

forcing all the plurality of reference voltages to be equal to the mid-reference voltage.

120. The method of claim 114 further comprising:

generating a first reference voltage and a second reference voltage dividing the 2^N voltage ranges into three groups of voltage ranges, a first one of the three groups of voltage ranges corresponding to the first group of one or more voltage ranges and being between the first and second reference voltages, a second one of the three groups of voltage ranges corresponding to the second group of one or more voltage ranges and being below the second reference voltage, a third one of the three groups of voltage ranges being above the first reference voltage.

121. The method of claim 120 wherein the sensing step comprises N or more sensing cycles, the method further comprising:

generating a plurality of reference voltages for uniquely identifying each of the 2^N voltage ranges;

during a plurality of the N or more sensing cycles, forcing the plurality of reference voltages to be equal to a mid-reference voltage between the first voltage range and the 2^N voltage range;

during one of a remaining sensing cycles, forcing one of the plurality of reference voltages to be equal to the first reference voltage; and

during another of the remaining sensing cycles, forcing another of the plurality of reference voltages to be equal to the second reference voltage.

122. The method of claim 120 wherein the first one of the three groups of voltage ranges comprises a substantially fewer number of the 2^N voltage ranges than each of the second one and third one of the three groups of voltage ranges.

123. The method of claim 120 wherein the first one of the three groups of voltage ranges comprises a substantially greater number of the 2^N voltage ranges than the second one and third one of the three groups of voltage ranges.

124. The method of claim 123 wherein the third one of the three groups of voltage ranges comprises the voltage range corresponding to the erased state, the second one of the three groups of voltage ranges comprises the voltage range corresponding to the 2^N voltage range, and the first one of the three groups of voltage ranges comprises all the remaining 2^N voltage ranges.

125. The method of claim 113 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

126. The method of claim 113 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

127. The method of claim 113 wherein N is greater than 2.

128. A multilevel memory comprising:

an array of memory cells each being capable of storing N bits of data by setting a state of the cell to within one of 2^N voltage ranges, N being an integer greater than 1; and

a first circuit configured to receive a plurality of reference voltages and one of a plurality of predefined margin sensing voltages, the plurality of reference voltages uniquely identifying each of the 2^N voltage ranges, the first circuit performing an arithmetic operation on the reference voltages and the one of the plurality of predefined margin sensing voltages, and providing a modified plurality of reference voltages for use in sensing operations.

129. The memory of claim 128 wherein the sensing operation corresponds to a read operation or a programming-verify operation.

130. The memory of claim 128 wherein the first circuit adds the one of the plurality of predefined margin sensing values to each of the plurality of reference voltages.

131. The memory of claim 128 wherein the first circuit subtracts the one of the plurality of predefined margin sensing values from each of the plurality of reference voltage levels.

132. The memory of claim 128 further comprising:

a reference voltage generator configured to generate the plurality of reference voltages; and

a precision margin generator configured to generate the one of the plurality of predefined margin sensing voltage values.

133. The memory of claim 132 wherein the reference voltage generator further comprises:

a reference circuit for generating a first set of reference voltages;

a plurality of reference memory cells for generating a second set of reference voltages; and

a multiplexer for selecting one of the first and second sets of reference voltages as the plurality of reference voltages for transfer to the first circuit.

134. The memory of claim 133 wherein the multiplexer is configured to force a predetermined number of the selected one of the first and second sets of reference voltages to a predetermined subset of the selected one of the first and second sets of reference voltages.

135. The memory of claim 128 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

136. The memory of claim 128 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

137. The memory of claim 128 wherein N is greater than 2.

138. A multilevel memory comprising:

an array of memory cells each being capable of storing N bits of data by setting a state of the cell to within one of 2^N voltage ranges, N being an integer greater than 1; and

a first circuit configured to receive a plurality of reference voltages uniquely identifying each of the 2^N voltage ranges, the first circuit being capable of reconfiguring the plurality of reference voltages to reduce the 2^N voltage ranges to less than 2^N ranges so that the storage capability of each cell is reduced from storing N bits.

139. The memory of claim 138 wherein the first circuit is capable of reconfiguring the plurality of reference voltages so that the 2^N voltage ranges are reduced to a first voltage range corresponding to an erased state and a second voltage range corresponding to a programmed state.

140. The memory of claim 139 wherein the first circuit is capable of reducing the 2^N voltage ranges to the first and second voltage ranges by forcing all the plurality of reference voltages to be equal to one reference voltage level.

141. The memory of claim 138 wherein the first circuit reconfigures the plurality of reference voltages so that the 2^N voltage ranges is reduced to three voltage ranges, a first voltage range corresponding to an intermediate margin voltage range, a second voltage range corresponding to a programmed state, and a third voltage range corresponding to an erased state.

142. The memory of claim 138 wherein the first circuit reconfigures the plurality of reference voltages so that the 2 voltage ranges is reduced to three voltage ranges, a first voltage range corresponding to failing states, a second voltage range corresponding to a programmed state, and a third voltage range corresponding to an erased state.

143. The memory of claim 138 wherein the first circuit comprises:

a second circuit for selecting one of a first set and a second set of reference voltages; and

a third circuit configured to receive the selected one of the first and second sets of reference voltages and one of a plurality of predefined margin sensing voltages, the selected one of the first and second sets of reference voltages uniquely identifying each of the 2^N voltage ranges, the third circuit performing an arithmetic operation on the selected one of the first and second sets of reference voltages and the one of the plurality of predefined margin sensing voltages, and providing a modified plurality of reference voltages for use in sensing operations.

144. The memory of claim 143 wherein the second circuit is configured to force a predetermined number of the selected one of the first and second sets of reference voltages to a predetermined subset of the selected one of the first and second sets of reference voltages.

145. The memory of claim 143 wherein the third circuit is configured to force a predetermined number of the selected one of the first and second sets of reference voltages to a predetermined subset of the selected one of the first and second sets of reference voltages.

146. The memory of claim 138 wherein each of the 2^N voltage ranges has a magnitude less than 150 mV.

147. The memory of claim 138 wherein the multilevel memory is a nonvolatile memory and is an integrated circuit.

148. The memory of claim 138 wherein N is greater than 2.