Self test of an electronic device

• US 6,397,042 B1
• Filed: 03/02/1999
• Issued: 05/28/2002
• Est. Priority Date: 03/06/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Izzard, Martin J., Prentice, Richard M.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): BEAMER, TEMICA M
• Application Number:
  US09/260,600
• Time in Patent Office: 1,183 Days
• Field of Search: 455/423,424,425,67.1,67.4,115,226.1,260,73 375/370,371,226,221,376,355 370/249 708/313 327/141,147,156
• US Class Current: 455/67.14
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back

Abstract

The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device (50) includes a transmit serializer (16), a transmit output buffer (13), a first phase interpolator (52), a phase locked loop (42), a second phase interpolator (44), a receive deserializer (18), a receive input buffer (15), and phase adjust logic (46). The PLL (42) generates a timing signal in accordance with a reference clock signal (43). In one mode of operation, the transmit serializer (16) transmits data for output through the transmit output buffer (13) in accordance with the timing signal generated by the PLL (42). In another mode of operation, the phase interpolator (52) accepts as input the timing signal generated by the PLL (42). The phase interpolator (52) then generates an altered timing signal which the transmit serializer (16) uses to transmits data for output through the transmit output buffer (13) asynchronously from the timing signal of the receive deserializer (18).

Claims

1. In an integrated circuit device including a data transmitter and a data receiver, the integrated circuit device comprising:

a clock source, having an output for a clock signal;

a phase locked loop, having an input connected to the output of the clock source, and having an output for providing a clock signal phase locked to a received signal and connected to the receiver for control of the timing of processing of the received data signal;

a phase interpolator having an input connected to the output of the clock source, having a control input for receiving control signals and adjusting the direction and rate of the phase interpolator in accordance with the control signals, and having an output providing a phase shifted clock signal and connected to the transmitter for control of the timing of processing of transmitted data signals.

2. An integrated circuit according to claim 1 wherein said phase locked loop comprises:

a second phase interpolator, having an input connected to the output of the clock source, having a control input for receiving a control word and adjusting the phase shift of the phase interpolator in accordance with the control word, and having an output providing a phase shifted clock signal and connected to the receiver for control of the timing of processing of received data signals; and

phase detect logic for detecting the difference in phase between the received data signals and the shifted clock signal, and providing a control word corresponding to the detected phase shift to the control input of the phase interpolator, a method for testing the integrated circuit device.

3. In an integrated circuit device including a data transmitter and a data receiver, the integrated circuit device comprising

a clock source, having an output for a clock signal;

a first phase interpolator, having an input connected to the output of the clock source, having a control input for receiving a control word and adjusting the phase shift of the phase interpolator in accordance with the control word, and having an output providing a phase shifted clock signal and connected to the receiver for control of the timing of processing of received data signals; and

phase detect logic for detecting the difference in phase between the received data signals and the shifted clock signal, and providing a control word corresponding to the detected phase shift to the control input of the phase interpolator, a method for testing the integrated circuit device;

a second phase interpolator having an input connected to the output of the clock source, having a control input for receiving control signals and adjusting the direction and rate of the phase interpolator in accordance with the control signals, and having an output providing a phase shifted clock signal and connected to the transmitter for control of the timing of processing of transmitted data signals;

a method for testing the integrated circuit device comprising the steps of;

applying control signals to said second phase interpolator to control the phase shift of the second phase interpolator at a constant rate in a selected direction so as to create a constant frequency offset to the phase shifted clock signal; and

measuring the response of the integrated circuit device to the effects of said control signals.