Signal processing apparatus and communication apparatus

• US 6,397,048 B1
• Filed: 07/20/1999
• Issued: 05/28/2002
• Est. Priority Date: 07/21/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Toda, Manabu
• Primary Examiner(s): Hunter, Daniel
• Assistant Examiner(s): Corsaro, Nick
• Application Number:
  US09/357,811
• Time in Patent Office: 1,043 Days
• Field of Search: 455/307,260,265,131 375/324,316,340,350
• US Class Current: 455/131
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H03H 17/0621 with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing

Abstract

An object of the present invention is to integrate circuits for frequency conversion processing of an input signal of the GHz band. In a receiver, an input signal from an antenna is amplified after components thereof outside a frequency band for communication network being removed, and is supplied to an arithmetic processing unit. A plurality of sampling circuits within the arithmetic processing unit respond to a plurality of clock signals of which frequencies are equal and of which phases are different, respectively, and sample the input signal after amplification. The sum-of-products arithmetic unit within the arithmetic processing unit responds any one of the clock signals and performs sum-of-products operation periodically using a plurality of sample signals exhibiting the sampling results of all the sampling circuits, respectively. A signal outputted from the sum-of-products arithmetic unit includes a reflected component equivalent to the component within the frequency band of the input signal being frequency-converted. A channel selection unit extracts the reflected component from the signal and converts the carrier frequency of the reflected component into an intermediate frequency. A reflected component after conversion is demodulated.

Claims

1. A signal processing apparatus comprising:

clock signal generating means for generating a plurality of clock signals of which frequencies are mutually equal and of which phases are different from each other;

a plurality of sampling means to which an input signal including signal components as processing objects within a predetermined input frequency band is supplied in parallel, which sampling means samples the input signal according to any one of the plurality of clock signals and outputs the sampled input signal sequentially as a sample signal;

sum-of-products operating means for periodically finding, with a timing based on an operating frequency which is equal to the frequency of the plurality of clock signals, a total sum of products of each of the sample signals outputted from all of the sampling means respectively and each of a plurality of predetermined multiplication coefficients; and

output filter means for only passing components within an output frequency band which is different from the input frequency band, in a sum-of-products signal which is constituted of the total sums of products aligned in order of being found.

2. The signal processing apparatus of claim 1, further comprising:

multiplication coefficient changing means for changing each of the plurality of multiplication coefficients.

3. The signal processing apparatus of claim 1, further comprising:

a plurality of re-sampling means interposed between the plurality of sampling means and the sum-of-products operating means, respectively, for sampling the sample signal outputted from each of the sampling means based on a clock signal delayed in phase from the clock signal supplied to each of the sampling means to output it to the sum-of-products operating means,

wherein the clock signals supplied to each of the sampling means are mutually equal.

4. The signal processing apparatus of claim 1,

wherein the frequency of the clock signals is equal to or less than twice the upper limit frequency of the input frequency band;

and

the output frequency band is lower than the input frequency band.

5. The signal processing apparatus of claim 1, further comprising:

buffer amplification means provided in the previous stage of all of the sampling means.

6. The signal processing apparatus of claim 1, further comprising:

halt indication means for indicating a halt of sampling of the input signal,

wherein the clock signal generating means halts the generation of clock signals while the halt indication means indicates the halt of sampling.

7. The signal processing apparatus of claim 1,

wherein the plurality of clock signals are 4-phase clock signals.

8. The signal processing apparatus of claim 1, further comprising:

a plurality of memory elements which are respectively connected in series to the next stage of each of the sampling means,

wherein each of the sampling means supplies the sample signal to the sum-of-products operating means and at the same time stores the sample signal in the memory element in the next stage of the sampling means, and

each of the memory elements transfers the stored sample signal to the memory element of the next stage to store therein, with a timing defined based on the clock signal supplied to each of the sampling means in the previous stage of each of the memory elements, and gives the sample signal to the sum-of-products operating means.

9. A communication apparatus comprising:

receiving means for receiving the input signal;

the signal processing apparatus of claim 1; and

demodulation means for demodulating an output signal outputted from the output filter means in the signal processing apparatus.

10. The communication apparatus of claim 9, further comprising:

intermediate filter means provided in the previous stage of the plurality of sampling means; and

a plurality of intermediate sampling means interposed between the receiving means and the intermediate filter means,

wherein each of the intermediate sampling means samples the input signal according to any one of all the clock signals, respectively, and sequentially outputs part of the input signal as an intermediate sample signal;

each of the intermediate filter means only passing signal components within a predetermined passing frequency band in an intermediate signal constructed by aligning the intermediate sample signals outputted from all of the intermediate sample means respectively in order of being sampled; and

each of the sampling means samples the signal components within the passing frequency band in the intermediate signal.

11. The communication apparatus of claim 10, further comprising:

detector means for detecting amplitude modulation components in the input signal; and

filter controlling means which discriminates whether interference components interfering the signal components as processing objects are included in the input signal based on the detected amplitude modulation components, and only when the interference components are included, changes frequency characteristics of at least any one of the sum-of-products operating means, the intermediate filter means and the output filter means, to frequency characteristics for removing the interference components.

12. The communication apparatus of claim 9,

wherein a frequency of the output signal is equal to an effective sampling frequency which is the product of the frequency of the clock signals and the number of the sampling means, or equal to the frequency which is one integers of the effective sampling frequency.

13. The communication apparatus of claim 12, wherein an order of the sum-of-products operating means which is smaller by one than a number of sample signals used for one-time arithmetic processing thereof is smaller than a decimation number which is a ratio of the frequency of the sum-of-products signal to the frequency of a multiphase sample signal constructed by aligning the sample signals in time order of being sampled.

14. The communication apparatus of claim 12, wherein the sum-of-products operating means performs arithmetic processing for implementing a finite impulse response FIR filter and that at least one of the plural multiplication coefficients in the arithmetic processing is zero.