Adaptive cell separation and circuit changes driven by maximum capacitance rules
First Claim
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1. A method for the placement of cells of a logic integrated circuit comprising the steps of:
- a) generating a netlist mapped to an area using a selected semiconductor technology, said netlist comprising a plurality of interconnected cells and associated nets, wherein each of said nets consists of the interconnect wires driven by its associated cell;
b) assigning a unit weight to each of said nets and establishing a convergence criterion;
c) performing a rough placement of said cells in accordance with the weights to produce an initial spacing between said cells;
d) evaluating the wire length associated with a net at the current cell spacing and adjusting the weights, said adjustment being determined from the synthesis library capacitance related parameters associated with said semiconductor technology;
e) performing a placement of the cells in accordance with the assigned weights f) repeating steps d) through e) for a predetermined number of times;
g) effecting changes to the netlist;
h) modifying said spacing;
i) defining partitions;
j) repeating steps d) through i) until said convergence criterion is met;
k) estimating timing parameters based upon node capacitances; and
l) performing a place and route process.
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Abstract
A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.
50 Citations
18 Claims
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1. A method for the placement of cells of a logic integrated circuit comprising the steps of:
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a) generating a netlist mapped to an area using a selected semiconductor technology, said netlist comprising a plurality of interconnected cells and associated nets, wherein each of said nets consists of the interconnect wires driven by its associated cell;
b) assigning a unit weight to each of said nets and establishing a convergence criterion;
c) performing a rough placement of said cells in accordance with the weights to produce an initial spacing between said cells;
d) evaluating the wire length associated with a net at the current cell spacing and adjusting the weights, said adjustment being determined from the synthesis library capacitance related parameters associated with said semiconductor technology;
e) performing a placement of the cells in accordance with the assigned weights f) repeating steps d) through e) for a predetermined number of times;
g) effecting changes to the netlist;
h) modifying said spacing;
i) defining partitions;
j) repeating steps d) through i) until said convergence criterion is met;
k) estimating timing parameters based upon node capacitances; and
l) performing a place and route process. - View Dependent Claims (2, 3, 4, 5, 6)
d1) dividing an available capacitive budget by said capacitance per unit length to give a first result;
d2) subtracting said first result of step d1) from said wire length to give a second result;
d3) dividing the second result of step d2) by said wire length to give a third result; and
d4) adding said third result of step d3) to said weight.
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7. A computer-readable medium having stored thereon instructions for causing a computer to implement a placement process comprising the steps of:
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a) generating a netlist mapped to an area using a selected semiconductor technology, said netlist comprising a plurality of interconnected cells and associated nets, wherein each of said nets consists of the interconnect wires driven by its associated cell;
b) assigning a unit weight to each of said nets and establishing a convergence criterion;
c) performing an rough placement of said cells in accordance with the weights to produce an initial spacing between said cells;
d) evaluating the wire length associated with a net at the current cell spacing and adjusting the weights, said adjustment being determined from the synthesis library parameters associated with said semiconductor technology;
e) performing a placement of the cells in accordance with the assigned weights f) repeating steps d) through e) for a predetermined number of times;
g) effecting changes to the netlist;
h) modifying said spacing;
i) defining partitions;
j) repeating steps d) through i) until said convergence criterion is met;
k) estimating timing parameters based upon node capacitances; and
l) performing a place and route process. - View Dependent Claims (8, 9, 10, 11, 12)
d1) dividing an available capacitive budget by said capacitance per unit length to give a first result;
d2) subtracting said first result of step d1) from said wire length to give a second result;
d3) dividing the second result of step d2) by said wire length to give a third result; and
d4) adding said third result of step d3) to said weight.
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13. A computer system having a bus, a memory coupled to the bus for storing instructions, a processor coupled to the bus for processing the instructions comprising the steps of:
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a) generating a netlist mapped to an area using a selected semiconductor technology, said netlist comprising a plurality of interconnected cells and associated nets, wherein each of said nets consists of the interconnect wires driven by its associated cell;
b) assigning a unit weight to each of said nets and establishing a convergence criterion;
c) performing an rough placement of said cells in accordance with the weights to produce an initial spacing between said cells;
d) evaluating the wire length associated with a net at the current cell spacing and adjusting the weights, said adjustment being determined from the synthesis library parameters associated with said semiconductor technology;
e) performing a placement of the cells in accordance with the assigned weights f) repeating steps d) through e) for a predetermined number of times;
g) effecting changes to the netlist;
h) modifying said spacing;
i) defining partitions;
j) repeating steps d) through i) until said convergence criterion is met;
k) estimating timing parameters based upon node capacitances; and
l) performing a place and route process. - View Dependent Claims (14, 15, 16, 17, 18)
d1) dividing an available capacitive budget by said capacitance per unit length to give a first result;
d2) subtracting said first result of step d1) from said wire length to give a second result;
d3) dividing the second result of step d2) by said wire length to give a third result; and
d4) adding said third result of step d3) to said weight.
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Specification
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Current AssigneeSynopsys Incorporated
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Original AssigneeSynopsys Incorporated
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InventorsIyer, Mahesh A., Shenoy, Narendra V., Ma, Hi-Keung, Damiano, Robert F., Harer, Kevin M.
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Primary Examiner(s)Teska, Kevin J.
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Assistant Examiner(s)THOMSON, WILLIAM D
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Application NumberUS09/109,988Time in Patent Office1,428 DaysField of Search703/13,14,15,16,17,19,3,20 716/5,9,10,12,13,2,6,7,8US Class Current703/14CPC Class CodesG06F 30/392 Floor-planning or layout, e...
