Reconfigurable memory with selectable error correction storage

• US 6,397,290 B1
• Filed: 08/17/2001
• Issued: 05/28/2002
• Est. Priority Date: 07/22/1999
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Williams, Brett L., Baldwin, Donald D.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/932,242
• Publication Number:
  US 20020029316A1
• Time in Patent Office: 284 Days
• Field of Search: 711/100,103,105,153,154,170 714/704,708,723,764,48 713/100
• US Class Current: 711/105
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction

Abstract

A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

Claims

1. A memory control system for a computer system having a memory array divisible into a plurality of memory partitions, comprising:

a memory controller responsive to an error intolerance signal for selectively assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, or error correction code partitions for error intolerant memory partitions;

a memory controller responsive to an error intolerance signal for selectively assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, or error correction code partitions for error intolerant memory partitions;

an error correction code unit for generating and processing sets of error correction codes for data stored in each of the error intolerant memory partitions; and

a data routing system operably connected to the memory array and the error correction code unit for routing the sets of error correction codes for the data stored in the error intolerant memory partitions to the corresponding error correction code partitions and retrieving the sets of error correction codes for the data stored in the error intolerant memory partitions from the corresponding error correction code partitions.

2. The memory control system of claim 1 further comprising an error correction code memory bank operably connected to the data routing system, the error correction code memory bank comprising a plurality of error correction code memory bank partitions.

3. The memory control system of claim 2 wherein the memory controller selectively assigns either a corresponding error correction code partition or a corresponding error correction code memory bank partition for storing the sets of error correction codes for each of the error intolerant memory partitions.

4. The memory control system of claim 3 wherein the data routing system selectively routes the set of error correction codes for the data stored in the error intolerant conventional memory partition to and from the corresponding error correction code partition or the corresponding error correction code memory bank partition.

5. The memory control system of claim 4 wherein the data routing system comprises:

a data bus;

a first switching circuit having a first data port coupled to the memory partitions assigned as error correction code partitions, a second data port coupled to the data bus, a third data port coupled to the error correction unit, and a mode select input, the switching circuit responsive to a first mode select signal to couple the first data port to the second data port, and responsive to a second mode select signal to couple the first data port to the third data port; and

a second switching circuit having a first data port coupled to the third data port of the first switching circuit, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second switching circuit responsive to a first control signal to couple the first data port to the third data port, and responsive to a second control signal to couple the second data port to the third data port.

6. The memory control system of claim 4 wherein the data routing system comprises:

a first multiplexer having a first data port coupled to the memory partitions assigned as error correction code partitions, a second data port coupled to the data bus, a third data port, and a control input, the first multiplexer responsive to a first control signal applied to the control input to couple the first data port to the second data port, and responsive to a second control signal to couple the first data port to the third data port; and

a second multiplexer having a first data port coupled to the third data port of the first multiplexer, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second multiplexer responsive to a third control signal applied to the control input to couple the first data port to the third data port, and responsive to a fourth control signal to couple the second data port to the third data port.

7. The memory control system of claim 5 wherein the data ports of the first switching circuit comprise a first plurality of sets of data lines, and the second data port of the second switching circuit comprises a second plurality of sets of data lines, the second switching circuit responsive to the first control signal to couple one of the sets in the first plurality of sets of data lines to the error correction unit, and responsive to the second control signal to couple one of the sets in the second plurality of sets of data lines to the error correction unit.

8. A memory for a computer system, comprising:

a memory array divisible into a plurality of memory partitions;

a memory controller responsive to an error intolerance signal for selectively assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, or error correction code partitions for corresponding error intolerant memory partitions;

an error correction code unit for generating and processing sets of error correction codes for data stored in each of the error intolerant memory partitions; and

a data routing system operably connected to the memory array and the error correction code unit for routing the sets of error correction codes for the data stored in the error intolerant memory partitions to the corresponding error correction code partitions and retrieving the set of error correction codes for the data stored in the error intolerant memory partitions from the corresponding error correction code partitions.

9. The memory of claim 8 further comprising an error correction code memory bank operably connected to the data routing system, the error correction code memory bank comprising a plurality of error correction code bank partitions.

10. The memory of claim 9 wherein the memory controller selectively assigns either a corresponding error correction code partition or a corresponding error correction code memory bank partition for storing the sets of error correction codes for each of the error intolerant memory partitions.

11. The memory of claim 10 wherein the data routing system selectively routes the set of error correction codes for the data stored in the error intolerant conventional memory partition to and from the corresponding error correction code partition or the corresponding error correction code memory bank partition.

12. The memory of claim 11 wherein the data routing system comprises:

a data bus;

a first switching circuit having a first data port coupled to the memory partitions assigned as error correction code partitions, a second data port coupled to the data bus, a third data port coupled to the error correction unit, and a mode select input, the switching circuit responsive to a first mode select signal to couple the first data port to the second data port, and responsive to a second mode select signal to couple the first data port to the third data port; and

a second switching circuit having a first data port coupled to the third data port of the first switching circuit, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second switching circuit responsive to a first control signal to couple the first data port to the third data port, and responsive to a second control signal to couple the second data port to the third data port.

13. The memory of claim 11 wherein the data routing system comprises:

a first multiplexer having a first data port coupled to the memory partitions assigned as error correction code memory bank partitions, a second data port coupled to the data bus, a third data port, and a control input, the first multiplexer responsive to a first control signal applied to the control input to couple the first data port to the second data port, and responsive to a second control signal to couple the first data port to the third data port; and

a second multiplexer having a first data port coupled to the third data port of the first multiplexer, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second multiplexer responsive to a third control signal applied to the control input to couple the first data port to the third data port, and responsive to a fourth control signal to couple the second data port to the third data port.

14. The memory of claim 12 wherein the data ports of the first switching circuit comprise a first plurality of sets of data lines, and the second data port of the second switching circuit comprises a second plurality of sets of data lines, the second switching circuit responsive to the first control signal to couple one of the sets in the first plurality of sets of data lines to the error correction unit, and responsive to the second control signal to couple one of the sets in the second plurality of sets of data lines to the error correction unit.

15. A computer system, comprising:

a data bus;

a plurality of peripheral devices;

a memory system having a memory array divisible into a plurality of memory partitions coupled to the data bus;

a memory controller responsive to an error intolerance signal for selectively assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, and selectively able to assign error correction code partitions for corresponding error intolerant memory partitions

an error correction code unit including a memory correction port, the error correction code unit generating and processing sets of error correction codes for data stored in each of the error intolerant memory partitions;

a processor coupled to the plurality of peripheral devices, the memory correction port and the data bus, the processor structured to couple data to or from the data bus and a corresponding error correction code to or from the memory correction port, respectively; and

a data routing system operably connected to the memory array and the error correction code unit for routing the sets of error correction codes for the data stored in the error intolerant memory partitions to the corresponding error correction code partitions and retrieving the set of error correction codes for the data stored in the error intolerant memory partitions from the corresponding error correction code partitions.

16. The computer system of claim 15 further comprising an error correction code memory bank operably connected to the data routing system, the error correction code memory bank comprising a plurality of error correction code memory bank partitions.

17. The computer system of claim 16 wherein the memory controller selectively assigns either a corresponding error correction code partition or a corresponding error correction code memory bank partition for storing the sets of error correction codes for each of the error intolerant memory partitions.

18. The computer system of claim 17 wherein the data routing system selectively routes the set of error correction codes for the data stored in the error intolerant conventional memory partition to and from the corresponding error correction code partition or the corresponding error correction code memory bank partition.

19. The computer system of claim 18 wherein the data routing system comprises:

a first switching circuit having a first data port coupled to the memory partitions assigned as error correction code partitions, a second data port coupled to the data bus, a third data port coupled to the error correction unit, and a mode select input, the switching circuit responsive to a first mode select signal to couple the first data port to the second data port, and responsive to a second mode select signal to couple the first data port to the third data port; and

a second switching circuit having a first data port coupled to the third data port of the first switching circuit, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second switching circuit responsive to a first control signal to couple the first data port to the third data port, and responsive to a second control signal to couple the second data port to the third data port.

20. The computer system of claim 18 wherein the data routing system comprises:

a first multiplexer having a first data port coupled to the memory partitions assigned as error correction code memory bank partitions, a second data port coupled to the data bus, a third data port, and a control input, the first multiplexer responsive to a first control signal applied to the control input to couple the first data port to the second data port, and responsive to a second control signal to couple the first data port to the third data port; and

a second multiplexer having a first data port coupled to the third data port of the first multiplexer, a second data port coupled to the error correction code memory bank, a third data port coupled to the error correction unit, and a control input, the second multiplexer responsive to a third control signal applied to the control input to couple the first data port to the third data port, and responsive to a fourth control signal to couple the second data port to the third data port.

21. The computer system of claim 19 wherein the data ports of the first switching circuit comprise a first plurality of sets of data lines, and the second data port of the second switching circuit comprises a second plurality of sets of data lines, the second switching circuit responsive to the first control signal to couple one of the sets in the first plurality of sets of data lines to the error correction unit, and responsive to the second control signal to couple one of the sets in the second plurality of sets of data lines to the error correction unit.

22. A method of storing and retrieving data in a memory system operable in either an error tolerant mode or an error intolerant mode, the method comprising:

dividing a memory array associated with the memory system into a plurality of memory partitions;

assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, or error correction code partitions for corresponding error intolerant memory partitions;

generating and processing sets of error correction codes for data stored in each of the error intolerant memory partitions; and

routing the sets of error correction codes for the data stored in the error intolerant memory partitions to the corresponding error correction code partitions and retrieving the sets of error correction codes for the data stored in the error intolerant memory partitions from the corresponding error correction code partitions.

23. The method of claim 22 further comprising operably connecting to the memory system an error correction code memory bank comprising a plurality of error correction code memory bank partitions.

24. The method of claim 23 further comprising selectively assigning either a corresponding error correction code partition or a corresponding error correction code memory bank partition for storing the sets of error correction codes for each of the error intolerant memory partitions.

25. The method of claim 24 further comprising selectively routing the set of error correction codes for the data stored in the error intolerant conventional memory partition to and from the corresponding error correction code partition or the corresponding error correction code memory bank partition.

26. A method of storing and retrieving data in a memory system operable in either an error tolerant mode or an error intolerant mode, the method comprising:

dividing a memory array associated with the memory system into a plurality of memory partitions;

assigning each of the memory partitions as error tolerant memory partitions, error intolerant memory partitions, or error correction code partitions for corresponding error intolerant memory partitions;

generating a set of error correction codes for data residing in an error intolerant memory partition;

storing the set of error correction codes for the data residing in the error intolerant memory partition in a corresponding error correction code partition;

reading the set of error correction codes stored in the corresponding error correction code partition when the data residing in the error intolerant memory partition is read;

determining from the set of error correction codes stored in the corresponding error correction code partition if the data residing in the error intolerant memory partition contains errors; and

correcting the errors determined in the data residing in the error intolerant memory partition.

27. The method of claim 26 further comprising operably connecting an error correction code memory bank to the memory system and dividing the error correction code memory banks into error correction code memory bank partitions.

28. The method of claim 27 further comprising storing the set of error correction codes for the data residing in the error intolerant memory partition in either a corresponding error correction code partition or an error code correction memory bank partition.

29. The method of claim 28 further comprising reading of the set of error correction codes for data residing in the error intolerant memory partition from either the corresponding error code correction partition or the error code correction memory bank partition where the set of error correction codes for the data residing in the error intolerant memory partition was stored.