Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system

• US 6,397,302 B1
• Filed: 06/18/1998
• Issued: 05/28/2002
• Est. Priority Date: 06/18/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Keller, James B., Razdan, Rahul, Kessler, Richard E.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Peugh, Brian R.
• Application Number:
  US09/099,304
• Time in Patent Office: 1,440 Days
• Field of Search: 711/120,143,144,118,146,133,134,141,142,145
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831

Abstract

A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiprocessor system. A processor of the multiprocessor system is configurable to evict from its cache a block of data. The selected block may have a clean coherence state or a dirty coherence state. The processor communicates a notify signal indicating eviction of the selected block to the memory controller. In addition to sending a write victim notify signal if the selected block has a dirty coherence state, the processor sends a clean victim notify signal if the selected block has a clean coherence state.

Claims

1. A computing apparatus, comprising:

a cache including a plurality of blocks;

an evictor unit configured to select a first block of data having an unmodified coherence state from the plurality of blocks to remove from the cache;

a signaling unit configured to transmit a notify signal to an external system indicating the removal of the first block from the cache;

a victim buffer storing the data associated with the first block of data selected by the evictor unit, the buffer being programmably configurable so that the external system can independently control pulling of the data associated with the first block from the buffer for transmission over the data bus to the external system and releasing of the data associated with the first block from the buffer; and

wherein the unmodified coherence state of the first block in the cache is a clean coherence state and the notify signal is a clean victim signal.

2. The computing apparatus of claim 1, wherein:

the evictor unit and the signaling unit are included in an external unit having an interface for communication of information to an external system.

3. The computing apparatus of claim 1, wherein:

the cache is one of an L1 cache and an L2 cache.

4. The computing apparatus of claim 1, wherein:

the evictor unit is further configured to select a second block from the plurality of blocks, the second block having a modified coherence state; and

the signaling unit is further configured to transmit another notify signal indicating removal of the second block from the cache.

5. The computing apparatus of claim 4, wherein the modified coherence state of the second block in the cache is a dirty coherence state and the another notify signal is a write victim signal.

6. The computing apparatus of claim 4, further comprising:

an address bus,

wherein the evictor unit is further configured to transmit an address associated with the first block and an address associated with the second block onto the address bus.

7. The computing apparatus of claim 6, further comprising:

a data bus,

wherein the evictor unit is further configured to transmit data associated with the first block and data associated with the second block onto the data bus.

8. The computing apparatus of claim 7, wherein

the transmitted address, the transmitted data, and the transmitted notify signals are received by an external system supporting a cache coherence protocol for the plurality of processors.

9. A computing apparatus, comprising:

first cache including a plurality of blocks of data; and

a processor configured to select a block of data of the plurality of blocks of data to evict from the first cache, the selected block having one of a clean coherence state and a dirty coherence state, to communicate a signal indicating eviction of the selected block to an external system managing caches of a multiprocessor system, including the first cache, and to communicate the eviction of the selected block to the external system by a clean victim signal if the selected block has a clean coherence state and a write victim signal if the selected block has a dirty coherence state;

wherein

the processor further includes a victim buffer configured to receive data of the selected block, the victim buffer being configured so that the external system can independently pull and release the data of the selected block.

10. The computing apparatus of claim 9, wherein:

the data of the selected block is pulled by the external system over a data bus by signaling the processor to transfer the data.

11. The computing apparatus of claim 9, wherein:

the data of the selected block is released by the external system signaling the processor to deallocate the block from the victim buffer.

12. A method for supporting cache coherence protocols by presenting a clean victim signal to an external system, comprising the steps of:

selecting a block to evict from one of a plurality of caches;

removing the evicted block from the one of the plurality of caches, the evicted block having an unmodified cache state;

transmitting the address of the evicted block to an external system which maintains cache coherency for the plurality of caches according to a cache protocol; and

communicating to the external system that the evicted block is unmodified;

receiving the data of the evicted block in a victim buffer; and

pulling the data of the evicted data block by the external system.

13. The method of claim 12, wherein:

an unmodified cache state is one of clean and clean shared.