Method of testing detection and correction capabilities of ECC memory controller

• US 6,397,357 B1
• Filed: 10/08/1996
• Issued: 05/28/2002
• Est. Priority Date: 10/08/1996
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Cooper, Steve
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US08/727,256
• Time in Patent Office: 2,058 Days
• Field of Search: 371/3,8.1,80.4,21.1,21.2,21.3,22.1,37.1,37.7,37.3,37.6,40.1,40.2,51.1,67.1 395/183.04,183.06,183.07,182.03,182.04 364/266,266.4,268,269.2,269.3,934.9,934.91,944
• US Class Current: 714/703
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

System and method for testing the error detection and correction (“ECC”) capabilities of an ECC memory controller are disclosed. The system uses the natural state of the bus to induce one- or two-bit memory errors by disabling the ECC capabilities of the controller and then writing a test data pattern that is one or two bits different than a data pattern that would result in an ECC code equal to the natural state of the bus and an ECC code equal to the natural state of the bus to a selected memory location. At that point, the ECC capabilities of the memory controller are reenabled and the memory location to which the test data pattern was previously written is read and its ECC code generated. A determination is then made whether the memory controller detected and/or corrected the induced error.

Claims

1. A method of verifying error checking and correction (“

ECC”

) capabilities of a memory controller electrically connected to a processor via a bus, said memory controller controlling access to a memory device, the method comprising;

disabling said ECC capabilities of said memory controller;

while said ECC capabilities of said memory controller are disabled, writing a test pattern and a first ECC code to a selected location in said memory device, said first ECC code corresponding to a natural state of said bus and said test pattern being at least one bit different than a pattern corresponding to said first ECC code, thereby inducing a memory error;

subsequent to said writing, enabling said ECC capabilities of said memory controller;

subsequent to said enabling, reading data stored at said selected memory location using said memory controller.

2. The method of claim 1 further comprising subsequent to said reading, determining whether said memory error was detected and corrected by said memory controller, wherein if said memory error was not detected and corrected by said memory controller, said memory controller is reported to have failed.

3. The method of claim 1 further comprising subsequent to said reading, determining whether said memory error was reported by said memory controller, wherein if said memory error was not detected and corrected by said memory controller, said memory controller is reported to have failed.

4. The method of claim 1 further comprising, subsequent to said reading, changing at least one test variable.

5. The method of claim 4 wherein said at least one test variable is selected from a group consisting of a memory location to which said test pattern is written, an identity of said test pattern, and a position within said test pattern of a bad bit.

6. The method of claim 1 wherein said memory error is a single bit error and said test pattern is one bit different than a pattern corresponding to said first ECC code.

7. The method of claim 1 wherein said memory error is a double bit error and said test pattern is two bits different than a pattern corresponding to said first ECC code.

8. The method of claim 1 further comprising replacing said memory controller if said memory controller is reported to have failed.

9. A computer program product for verifying error checking and correction (“

ECC”

) capabilities of a memory controller electrically connected to a processor via a bus, said memory controller controlling access to a memory device, the computer program product stored on a computer-readable medium and comprising;

instructions for disabling said ECC capabilities of said memory controller;

instructions for writing a test pattern and a first ECC code to a selected location in said memory device while said ECC capabilities of said memory controller are disabled, said first ECC code corresponding to a natural state of said bus and said test pattern being at least one bit different than a pattern corresponding to said first ECC code, thereby inducing a memory error;

instructions for enabling said ECC capabilities of said memory controller after said writing;

instructions for reading data stored at said selected memory location using said memory controller subsequent to said enabling.

10. The computer program product of claim 9 further comprising instructions for determining whether said memory error was detected and corrected by said memory controller subsequent to said reading, wherein said memory controller is reported to have failed if said memory error was not detected and corrected by said memory controller.

11. The computer program product of claim 9 further comprising instructions for determining whether said memory error was reported by said memory controller subsequent to said reading, wherein said memory controller is reported to have failed if said memory error was not detected and corrected by said memory controller.

12. The computer program product of claim 9 further comprising instructions for changing at least one test variable subsequent to said reading.

13. The computer program product of claim 12 wherein said at least one test variable is selected from a group consisting of a memory location to which said test pattern is written, an identity of said test pattern, and a position within said test pattern of a bad bit.

14. The computer program product of claim 9 wherein said memory error is a single bit error and said test pattern is one bit different than a pattern corresponding to said first ECC code.

15. The computer program product of claim 9 wherein said memory error is a double bit error and said test pattern is two bits different than a pattern corresponding to said first ECC code.

16. Apparatus for verifying error checking and correction (“

ECC”

) capabilities of a memory controller electrically connected to a processor via a bus and for controlling access to a memory device, the apparatus comprising;

means for disabling said ECC capabilities of said memory controller;

means for writing a test pattern and a first ECC code to a selected location in said memory device while said ECC capabilities of said memory controller are disabled, said first ECC code corresponding to a natural state of said bus and said test pattern being at least one bit different than a pattern corresponding to said first ECC code, thereby inducing a memory error;

means for enabling said ECC capabilities of said memory controller after said writing;

means for causing said memory controller to read data stored at said selected memory location subsequent to said enabling.

17. The apparatus of claim 16 further comprising:

means for determining whether said memory error was detected and corrected by said memory controller subsequent to said reading; and

means for indicating that said memory controller has failed if said memory error was not detected and corrected by said memory controller.

18. The apparatus of claim 16 further comprising:

means for determining whether said memory error was reported by said memory controller subsequent to said reading; and

means for indicating that said memory controller has failed if said memory error was not detected and corrected by said memory controller.

19. The apparatus of claim 16 further comprising means for changing at least one test variable subsequent to said reading.

20. The apparatus of claim 19 wherein said at least one test variable is selected from a group consisting of a memory location to which said test pattern is written, an identity of said test pattern, and a position within said test pattern of a bad bit.

21. The apparatus of claim 16 wherein said memory error is a single bit error and said test pattern is one bit different than a pattern corresponding to said first ECC code.

22. The apparatus of claim 16 wherein said memory error is a double bit error and said test pattern is two bits different than a pattern corresponding to said first ECC code.

23. In a computer comprising a memory controller electrically connected to a processor via a bus, said memory controller being for controlling access to a memory device and having error checking and correcting (“

ECC”

) capabilities, an apparatus for verifying the accuracy of said ECC capabilities of said memory controller, the apparatus comprising;

means for disabling said ECC capabilities of said memory controller;

means for writing a test pattern and a first ECC code to a selected location in said memory device while said ECC capabilities of said memory controller are disabled, said first ECC code corresponding to a natural state of said bus and said test pattern being at least one bit different than a pattern corresponding to said first ECC code, thereby inducing a memory error;

means for enabling said ECC capabilities of said memory controller after said writing;

means for causing said memory controller to read data stored at said selected memory location subsequent to said enabling;

means for determining, with respect to single bit memory errors, whether said memory error was detected and corrected by said memory controller subsequent to said reading and if not, indicating that said memory controller has failed; and

means for determining, with respect to double bit memory errors, whether said memory error was reported by said memory controller subsequent to said reading and if not, indicating that said memory controller has failed.