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Method of testing detection and correction capabilities of ECC memory controller

  • US 6,397,357 B1
  • Filed: 10/08/1996
  • Issued: 05/28/2002
  • Est. Priority Date: 10/08/1996
  • Status: Expired due to Term
First Claim
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1. A method of verifying error checking and correction (“

  • ECC”

    ) capabilities of a memory controller electrically connected to a processor via a bus, said memory controller controlling access to a memory device, the method comprising;

    disabling said ECC capabilities of said memory controller;

    while said ECC capabilities of said memory controller are disabled, writing a test pattern and a first ECC code to a selected location in said memory device, said first ECC code corresponding to a natural state of said bus and said test pattern being at least one bit different than a pattern corresponding to said first ECC code, thereby inducing a memory error;

    subsequent to said writing, enabling said ECC capabilities of said memory controller;

    subsequent to said enabling, reading data stored at said selected memory location using said memory controller.

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