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Reduced-pin integrated circuit I/O test

  • US 6,397,361 B1
  • Filed: 04/02/1999
  • Issued: 05/28/2002
  • Est. Priority Date: 04/02/1999
  • Status: Expired due to Term
First Claim
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1. A method for testing a chip comprising the steps of:

  • (a) providing a plurality of switches on the chip which are associated with a plurality of input/output circuits on the chip;

    (b) selectively changing the state of a predetermined number of the plurality of switches from a first state to a second state, (c) applying a test condition to a predetermined number of the plurality of input/output circuits on the chip through the plurality of switches; and

    (d) measuring a resultant condition from the predetermined number of input/output circuits to determine if any of the pre-determined number of input/output circuits on the chip are faulty.

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