Recording in a program execution profile references to a memory-mapped active device

• US 6,397,379 B1
• Filed: 10/28/1999
• Issued: 05/28/2002
• Est. Priority Date: 01/28/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Yates, Jr., John S., Reese, David L., Van Dyke, Korbin S.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): INGBERG, TODD D
• Application Number:
  US09/428,850
• Time in Patent Office: 943 Days
• Field of Search: 712/35,203,208 717/9,5
• US Class Current: 717/140
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.

Claims

1. A method, comprising the steps of:

as part of executing a stream of instructions, issuing a series of memory loads from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space;

recording in a storage of the computer addresses of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.

2. The method of claim 1, wherein the recording is a portion of a profile primarily recording program control flow.

3. The method of claim 1, further comprising reading the recording by a binary translation program, wherein the binary translation program translates the memory load using more conservative assumptions when the recording indicates that the memory load is directed to non-well-behaved memory.

4. A method, comprising the steps of:

issuing a successful memory reference from a computer CPU to a bus;

recording in a storage of the computer whether a device accessed over the bus by the memory reference is well-behaved memory or not-well-behaved memory.

5. The method of claim 4, further comprising the steps of:

as a program is executed by the computer CPU, monitoring memory write references to a well-behaved main memory of the computer and reporting detection of a memory write reference to a protected region in the main memory, the monitoring and reporting being performed by monitoring circuitry of the computer;

on receiving a report of the detection, deleting from the main memory a data structure whose content reflects the content of the protected region.

6. The method of claim 4, further comprising the steps of:

monitoring memory read references initiated by instructions executed by the computer CPU, the memory references referring to logical addresses;

as part of translating the logical address into a physical address, evaluating whether a main memory page of the reference is in a protected state;

if the page is unprotected, putting the page in a protected state.

7. The method of claim 4, further comprising the step of:

evaluating whether an individual memory reference of an instruction references a device that cannot be guaranteed to be well-behaved, and if the reference cannot be guaranteed to be well-behaved, re-executing the instruction in an alternative execution mode.

8. The method of claim 4, further comprising the steps of:

while translating at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture, using the recording to distinguish memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory;

while executing the translation into the second instruction set architecture, identifying loads that were believed at translation time to be directed to well-behaved memory but that at execution are found to be directed to non-well-behaved memory, and aborting the identified memory load;

re-executing at least a portion of the translated segment of the program in the first instruction set.

9. The method of claim 4, wherein references to I/O space are recorded as being references to non-well-behaved memory.

10. The method of claim 9, wherein the recording is slightly in error, the error being induced by a conservative estimate in determining when the memory reference accesses well-behaved memory.

11. The method of claim 4, wherein the form of the recording allows determination of whether the memory reference was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.

12. The method of claim 4, wherein the form of the recording indicates an address of an instruction that issued the memory reference.

13. The method of claim 4, wherein the memory reference is a load.

14. The method of claim 4, wherein the recording is a portion of a profile primarily recording program control flow.

15. The method of claim 4, further comprising reading the recording by a binary translation program.

16. The method of claim 15, wherein the binary translation program translates the memory reference using more conservative assumptions when the recording indicates that the memory reference is directed to non-well-behaved memory.

17. A computer, comprising:

a computer CPU designed to execute instructions, including generating memory read references on behalf of those instructions;

profile monitoring circuitry designed to generate a record of a memory read reference that references a device other than well-behaved memory.

18. The computer of claim 17, further comprising:

circuitry designed to monitor memory write references of the computer CPU, and to detect memory write references to a protected structure in a main memory of the computer;

hardware and/or software responsive to the detection by the circuitry, and designed to delete from main memory a data structure whose content reflects the content of the protected structure.

19. The computer of claim 17, further comprising:

address translation circuitry designed to translate logical addresses, generated as part of memory read accesses by a CPU of the computer, into physical addresses, and to evaluate whether a page of the address is protected against that access; and

circuitry and/or software responsive to the evaluation that the page is unprotected, and designed to put the page in a protected state.

20. The computer of claim 17, further comprising:

instruction execution circuitry designed to evaluate whether an individual memory reference of an instruction references memory that cannot be guaranteed to be well-behaved.

21. The computer of claim 20, further comprising:

circuitry designed to flush any pending side-effects of execution of an instruction, before those side effects are committed, when the evaluation circuitry determines that a memory reference references memory that cannot be guaranteed to be well-behaved.

22. The computer of claim 21, further comprising:

hardware and/or software designed to restart program execution in a mode in which the reference to memory that cannot be guaranteed to be well-behaved is guaranteed to be executed correctly.

23. The computer of claim 17, further comprising:

a translator programmed to translate a source program into an object program, wherein a sequence of side-effects in the object program differs from a reference sequence of side-effects in the source program;

circuitry and/or software designed to intervene during an execution of the object program on the computer to establish a program state equivalent to a state that would have occurred in the reference sequence, and to resume execution of the program from the established state in an execution mode that reflects the reference side-effect sequence.

24. The computer of claim 17, wherein the profile monitoring circuitry is designed to record a non-well-behaved reference using a conservative, slightly-incorrect approximation of well-behaved memory.

25. The computer of claim 17, wherein the profile monitoring circuitry is designed to generate a record in a form that does not require resolution of a memory address stored in the recording to determine whether the memory reference was to well-behaved memory or not-well-behaved memory.

26. The computer of claim 17, wherein the profile monitoring circuitry is interwoven with the computer CPU.

27. The computer of claim 17, further comprising a TLB (translation lookaside buffer) designed to hold a determination of whether memory mapped by entries of the TLB is well-behaved or non-well-behaved memory.

28. The computer of claim 17, wherein the profile monitoring circuitry generates the record into a general purpose register of the computer.

29. The computer of claim 17, wherein the profile monitoring circuitry is designed to induce a pipeline flush of the computer CPU when the other-than-well-behaved memory read reference is detected.

30. The computer of claim 17, wherein references to I/O space are recorded as being references to other than well-behaved memory.

31. The computer of claim 17, wherein references to memory regions recently overwritten by DMA (direct memory access) transfers are recorded as being references to other than well-behaved memory.

32. The computer of claim 17, wherein references to memory regions shared among multiple CPU'"'"'s are recorded as being references to other than well-behaved memory.

33. The computer of claim 17, wherein references to memory regions containing self-modifying code are recorded as being references to other than well-behaved memory.

34. The computer of claim 17, further comprising hardware and/or software designed to store the record in an execution profile of execution flow of a program executing on the computer.

35. The computer of claim 17, wherein the whether a memory reference is well-behaved or other than well-behaved is determined on the basis of memory pages.

36. A method, comprising the steps of:

issuing a successful memory reference from a computer CPU to a bus;

as part of the processing of the instruction that generated the memory reference, recording in a storage of the computer whether a device accessed over the bus by the memory reference is well-behaved memory or at least one of the following classes of memory-mapped devices that are other than well-behaved;

a device wherein a read of the device causes the device to change state, or

a device wherein a read does not necessarily return the value most-recently written to the same address as the memory reference, or

a device wherein two successive reads return distinct data.

37. The method of claim 36, further comprising the steps of:

as a program is executed by the computer CPU, monitoring memory write references to a well-behaved main memory of the computer and reporting detection of a memory write reference to a protected region in the main memory, the monitoring and reporting being performed by monitoring circuitry of the computer;

on receiving a report of the detection, deleting from the main memory a data structure whose content reflects the content of the protected region.

38. The method of claim 36, further comprising the steps of:

monitoring memory read references initiated by instructions executed by the computer CPU, the memory references referring to logical addresses;

as part of translating the logical address into a physical address, evaluating whether a main memory page of the reference is in a protected state;

if the page is unprotected, putting the page in a protected state.

39. The method of claim 36, further comprising the step of:

evaluating whether an individual memory reference of an instruction references a device that cannot be guaranteed to be well-behaved, and if the reference cannot be guaranteed to be well-behaved, re-executing the instruction in an alternative execution mode.

40. The method of claim 36, further comprising the steps of:

while translating at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture, using the recording to distinguish memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory;

while executing the translation into the second instruction set architecture, identifying loads that were believed at translation time to be directed to well-behaved memory but that at execution are found to be directed to non-well-behaved memory, and aborting the identified memory load;

re-executing at least a portion of the translated segment of the program in the first instruction set.

41. The method of claim 36, wherein the recording is slightly in error, the error being induced by a conservative estimate in determining when the memory reference accesses well-behaved memory.

42. The method of claim 36, wherein the memory reference is a load.

43. The method of claim 36, wherein the recording is a portion of a profile primarily recording program control flow.

44. The method of claim 36, further comprising reading the recording by a binary translation program.

45. The method of claim 44, wherein the binary translation program translates the memory reference using more conservative assumptions when the recording indicates that the memory reference is directed to non-well-behaved memory.

46. The method of claim 36, further comprising the step of:

recording in the storage of the computer whether a device accessed over the bus by the memory reference is well-behaved memory or at least two of the classes of memory-mapped devices that are other than well-behaved.

47. The method of claim 36, further comprising the step of:

recording in the storage of the computer whether a device accessed over the bus by the memory reference is well-behaved memory or at least some references of all three of the classes of memory-mapped devices that are other than well-behaved.