Method for producing a DRAM cell with a trench capacitor

• US 6,399,435 B1
• Filed: 10/15/2001
• Issued: 06/04/2002
• Est. Priority Date: 02/19/1999
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Tihanyi, Jenoe
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/913,422
• Time in Patent Office: 232 Days
• Field of Search: 438/243-249, 438/386-392
• US Class Current: 438/248
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

The present invention provides a method for fabricating a DRAM cell having a trench capacitor. In order to simplify the fabrication method for a DRAM cell, to ensure a high yield and to achieve a high packing density of the DRAM cells, the invention proposes that the storage capacitor (4) of the DRAM cell and the selection transistor (3) be fabricated independently of one another. This saves method steps which, in the prior art, have to be carried out in order to isolate capacitor (9) and gate (16) in the same trench.

Claims

1. A method for fabricating a DRAM memory cell having a trench capacitor, which comprises the steps of:

producing a first trench in a first zone of a first conductivity type, coating the surface of the first trench with a first insulator layer and filling the first trench with a conductive material of a second conductivity type, the first zone and the conductive material in the first trench being highly doped;

arranging a second zone of the first conductivity type on the first zone, so that the first trench is covered;

producing a region of the second conductivity type in the second zone by diffusion of dopant from the conductive material in the first trench;

etching adjacent regions next to the first trench, so that semiconductor material is removed proceeding from the surface of the second zone right into the first zone;

filling the adjacent regions with an insulator material, so that an insulator region is produced between adjacent trenches;

producing bit lines made of the conductive material of the second conductivity type and drain zones for selection transistors on the surface of the second zone;

producing the selection transistor in a second trench in the second zone above the first trench in the first zone; and

producing word lines made of the conductive material on the uncovered surface of the second zone.

2. The method as claimed in claim 1, wherein arranging the second zone on the first zone comprises the steps of “

Direct Wafer Bonding”

of the second zone on the first zone and thinning of the second zone to a predetermined thickness.

3. The method as claimed in claim 1, wherein the process of coating with an insulator layer is effected by oxidation of the semiconductor material.

4. The method as claimed in claim 1, wherein the adjacent regions of the first trench are filled by a thick oxide.

5. The method as claimed in claim 1, wherein the insulator material comprises a plurality of layers.