Semiconductor devices and methods for manufacturing semiconductor devices

• US 6,399,477 B2
• Filed: 02/03/2001
• Issued: 06/04/2002
• Est. Priority Date: 02/03/2000
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Morozumi, Yukio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US09/776,391
• Publication Number:
  US 20010034119A1
• Time in Patent Office: 486 Days
• Field of Search: 438/612, 438/620, 438/622, 438/624, 438/625, 438/626, 438/629, 438/631, 438/642, 438/648, 438/650, 438/686, 438/687, 438/688
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05576 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48639 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48739 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48744 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48747 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 : Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53233 : Copper alloys
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which a layer including at least a bonding pad section is formed by a damascene method, the method comprising the steps of: (a) forming an opening region 80a for the bonding pad section in an uppermost dielectric layer 22, the opening region being divided by dielectric layers 22a of a specified pattern and including a plurality of partial opening sections 81; (b) successively forming a plurality of conduction layers 820, 840 composed of different materials over the dielectric layer; and (c) removing excess portions of the plurality of conduction layers 820, 840 and the dielectric layer 22 to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section 80 in which a plurality of conduction layers 82, 84 composed of different materials are exposed in each of the partial opening sections 81 of the opening region 80a.

Claims

1. A method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method, the method comprising the steps of:

(a) forming an opening region for the bonding pad section in an uppermost dielectric layer, the opening region being divided by dielectric layers of a specified pattern and including a plurality of partial opening sections;

(b) successively forming a plurality of conduction layers comprising different materials over the dielectric layer; and

(c) removing excess portions of the plurality of conduction layers and the dielectric layer to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers comprising different materials are exposed in each of the partial opening sections of the opening region.

2. A method for manufacturing a semiconductor device according to claim 1, wherein, in the step (b), the plurality of conduction layers are formed to a film thickness that allows the plurality of conduction layers to remain after the step (c) of planarization.

3. A method for manufacturing a semiconductor device according to claim 1, wherein, in the step (a), a wiring groove for an uppermost wiring layer is formed in the uppermost dielectric layer together with the opening region for the bonding pad section.

4. A method for manufacturing a semiconductor device according to claim 3, wherein, in the step (b), the plurality of conduction layers include a conduction layer for the wiring layer.

5. A method for manufacturing a semiconductor device according to claim 4, wherein the conduction layer for the wiring layer is a lowermost layer among the plurality of conduction layers and deposited in the wiring groove.

6. A method for manufacturing a semiconductor device according to claim 5, wherein a conduction layer above the conduction layer for the wiring layer is deposited at least in the opening region for the bonding pad section.

7. A method for manufacturing a semiconductor device according to claim 1, further comprising, after the step (c), the steps of forming a dielectric protection layer and patterning the dielectric protection layer to have an opening section that exposes the bonding pad section.

8. A method for manufacturing a semiconductor device according to claim 1, wherein the layer including the bonding pad section is formed by a process selected from the group consisting of a single damascene process and a dual damascene process.

9. A method for manufacturing a semiconductor device according to claim 4, wherein the conduction layer for the wiring layer is formed from a layer comprising at least one metal selected from aluminum, copper, silver and a metal alloy thereof, and

an upper layer above the conduction layer for the wiring layer is formed from a material different from the conduction layer for the wiring layer, and the upper layer is formed from a layer comprising at least one metal selected from aluminum, gold and a metal alloy thereof.

10. A method for manufacturing a semiconductor device according to claim 1, further comprising, after the step (a), the step of forming at least one of a barrier layer and a cohesion layer over a surface of the opening region for the bonding pad section.

11. A method for manufacturing a semiconductor device according to claim 1, wherein, in the step (c), the step of planarization is conducted by a chemical-mechanical polishing method.

12. A method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method, the method comprising:

forming an opening region for the bonding pad section in a dielectric layer, the opening region comprising a plurality of sub-openings divided from one another by dielectric walls;

forming a plurality of conduction layers into at least two of the sub-openings; and

removing any excess portions of the plurality of conduction layers and the dielectric layer to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers are exposed in each of the sub-openings of the opening region.

13. A method for manufacturing a semiconductor device as in claim 12, wherein the plurality of conduction layers have different compositions.

14. A method for manufacturing a semiconductor device as in claim 12, wherein a plurality of conduction layers are formed into each of the sub-openings.

15. A method for manufacturing a semiconductor device as in claim 14, wherein the plurality of conduction layers have different compositions.